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| 型号： | IDT72V73273BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC DGTL SW 32768X32768 208-BGA |
| 标准包装： | 12 |
| 系列： | 72V |
| 类型： | 多路复用器 |
| 电路： | 8 x 1:1 |
| 电压电源： | 单电源 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-BGA |
| 供应商设备封装： | 208-PBGA（17x17） |
| 包装： | 托盘 |
| 其它名称： | 72V73273BBG |
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13
INDUSTRIAL TEMPERATURERANGE
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
TABLE 6 BER INPUT SELECTION REGISTER (BIS)
Reset Value:
Unknown (must be programmed)
15
14
13
12
11
10
9876543210
15
Unused
Mustbezerofornormaloperation
14-12
BG2-BG0
These bits refer to the input data group which receives the BER data.
((BER Input Group
AddressBits)
11-9
BSA2-BSA0
These bits refer to the input data stream which receives the BER data.
(BER Input
StreamAddressBits)
8-0
BCA8-BCA0
These bits refer to the input channel which receives the BER data.
(Local BER Input
ChannelAddressBits)
BIT
NAME
DESCRIPTION
0
BG2
BG1
BG0
BSA2
BSA1
BSA0
BCA8
BCA7
BCA6
BCA5
BCA4
BCA3
BCA2
BCA1
BCA0
TABLE 7 BIT ERROR RATE REGISTER (BERR)
Reset Value:
Unknown (must be programmed)
15
14
13
12
11
10
9876543210
15-0
BER15-BER0
Thesebitsrefertothelocalbiterrorcounts.
(Local Bit Error Rate
CountBits)
BIT
NAME
DESCRIPTION
BER15 BER14 BER13 BER12 BER11 BER10
BER9
BER8
BER7
BER6
BER5
BER4
BER3
BER2
BER1
BER0
BIT ERR
BIT ERROR RA
OR RA
OR RATE
TE
Pseudo-RandomBitSequences(PRBS)canbeindependentlytransmitted
andreceived. BysettingtheconnectionmemoryhighbitstotheBERtransmit
mode,thatparticularchannelwilltransmitaBERpatternoftheform215-1. For
thereceiveronlyonechannelcanbespecifiedandmonitoredatagiventime.
BysettingtheBERInputSelection(BIS)toagivenchannel,everyerrorinthe
BER sequence will be incremented by one.
If the more than 216-1 errors are encountered the BERR register will
automaticallyoverflowandberesettozero. Itisimportanttonotethatnointerrupt
or warning will be issued in this case. It is recommended that this register be
polled periodically and reset to prevent can overflow condition. To reset the
Pseudo-random bit sequence and the error count registers set the PRST,
CBER,andSBERoftheControlRegistertohigh. SeetheControlRegisterfor
details.
Following a write to the BERR register a read of the BERR will result in the
presentvalueoftheBERRdata. Likewise,whentheClearBitRatebit(CBER)
in the control register is activated, this will clear the internal BERR (iBERR).
Asageneralrule,areadofBERRshouldbeproceededbyawritetoBERR.
Again,itshouldbenotedthatthewritetotheBERRregisterwillactuallyinitiate
atransferfromtheiBERRtotheBERRwhilethemicroprocessordataisignored.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
all input data comes in at the same speed, delays can be caused by variable
pathserialbackplanesandvariablepathlengthswhichmaybeimplemented
inlargecentralizedanddistributedswitchingsystems.Becausedataisoften
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
clockperiodsforwardwitharesolutionofclockperiod,seeTable9.Theoutput
streamscannotbeadjusted.
NOTE:
Before a read of the BERR, a write to the BERR is necessary. As a read only register the write will have no effect. See the Bit Error Rate section for mor details
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