参数资料
型号: IDT79R3081-40DL8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84
封装: 0.050 INCH PITCH, HEAT SINK, PLASTIC, LCC-84
文件页数: 40/41页
文件大小: 893K
代理商: IDT79R3081-40DL8
IDT79R3081 RISController
MILITARY AND COMMERICAL TEMPERATURE RANGES
5.5
8
NOTES ON SYSTEM DESIGN
The R3081 has been designed to simplify the task of high-
speed system design. Thus, set-up and hold-time require-
ments have been kept to a minimum, allowing a wide variety of
system interface strategies.
To minimize these AC parameters, the R3081 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3081 to reference input signals to the
reference clock seen by the external system. The SysClk out-
put is designed to provide relatively large AC drive to
minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise or fall (10% to 90% signal times) when
driving the test load.
Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net and the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.
Similarly, the R3081 employs feedback on its ALE output to
ensure adequate address hold time to ALE. The system
designer should be careful when designing the ALE net to
minimize total loading and to minimize skew between ALE and
the A/D bus, which will ensure adequate address access latch
time.
IDT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.
Airflow (m/s)
01234
5
DL84 JA
21.0
12.8
12.0
9.9
9.2
8.5
DL84 CA
18.3
10.1
9.3
7.2
6.6
5.8
PL84 JA
36.6
29.6
27.0
26.2
25.4
24.8
PL84 CA
18.3
10.1
9.3
7.2
6.6
5.8
Table 1 Thermal Resistance at Various Airflows
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