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参数资料
| 型号： | IDT79R3081-40DL8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84 |
| 封装： | 0.050 INCH PITCH, HEAT SINK, PLASTIC, LCC-84 |
| 文件页数： | 41/41页 |
| 文件大小： | 893K |
| 代理商： | IDT79R3081-40DL8 |
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5.5
9
IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
PIN NAME
I/O
DESCRIPTION
A/D(31:0)
I/O
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
Address(31:4):
The high-order address for the transfer is presented on A/D(31:4).
BE
BE(3:0):
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on A/D(3:0).
During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data transaction
or in a burst of four words, and places it into the on-chip read buffer.
During cache coherency operations, the R3081 monitors the A/D bus at the start of a DMA write to capture
the write target address for potential data cache invalidates.
Addr(3:2)
O
Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at ‘00’ for burst read operations.
During cache coherency operations, the R3081 monitors the Addr bus at the start of a DMA write to
capture the write target address for potential data cache invalidates.
Diag(1)
O
Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an on-chip
cache miss, and also presents part of the miss address. The value output on this pin is time multiplexed:
Cached:
During the phase in which the A/D bus presents address information, this
pin is an active HIGH output which indicates whether the current read is
a result of a cache miss.
Miss Address (3):
During the remainder of the read operation, this output presents address
bit (3) of the address the processor was attempting to reference when the
cache miss occurred. Regardless of whether a cache miss is being
processed, this pin reports the transfer address during this time.
On write cycles, this output signals whether the data being written as retained in the on-chip data cache.
The value of this pin is time multiplexed during writes:
Cached:
During the address phase of write transactions, this signal is an active
high output which indicates that the store data was retained in the on-chip
data cache.
Reserved:
The value of this pin during the data phase of writes is reserved.
Diag(0)
O
Diagnostic Pin 0. This output distinguishes cache misses due to instruction references from those
due to data references, and presents the remaining bit of the miss address. The value output on this
pin is also time multiplexed:
I/
D
D:
If the “Cached” Pin indicates a cache miss, then a high on this pin at this
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.
Miss Address (2):
During the remainder of the read operation, this output presents
address bit (2) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
during this time.
During write cycles, the value of this pin during both the address and data phases is reserved.
2889 tbl 02
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT79R3081-40DLG | 制造商:Integrated Device Technology Inc 功能描述:MPU R3081 RISC 32-Bit 40MHz 84-Pin PLCC |
| IDT79R3081E25DL | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT79R4650-100DP | 功能描述:IC MPU 64BIT W/DSP 100MHZ 208QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| IDT79R4650-133DP | 功能描述:IC MPU 64BIT W/DSP 133MHZ 208QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| IDT79R4700-100DP | 功能描述:IC MPU 64BIT 5V 100MHZ 208-QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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