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| 型号： | IDT82V2048BBG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/62页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1 8CH SHORT 160-BGA |
| 标准包装： | 14 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 160-BGA |
| 供应商设备封装： | 160-PBGA（15x15） |
| 包装： | 托盘 |
| 其它名称： | 82V2048BBG |
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19
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
Figure-12 DSX-1 Waveform Template
Figure-13 CEPT Waveform Template
2.5.2
BIPOLAR VIOLATION INSERTION
When configured in Single Rail Mode 2 with AMI line code enabled,
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit
data stream. Sampling occurs on the falling edges of TCLK. But in TAOS
(Transmit All Ones) with Analog Loopback, Remote Loopback and
Inband Loopback, the BPVI is disabled. In TAOS with Digital Loopback,
the BPVI is looped back to the system side, so the data to be transmitted
on TTIPn and TRINGn are all ones with no bipolar violation.
2.6
JITTER ATTENUATOR
The jitter attenuator can be selected to work either in transmit path or
in receive path or not used. The selection is accomplished by setting pin
JAS in hardware mode or configuring bits JACF[1:0] in register GCF in
host mode, which affects all eight channels.
For applications which require line synchronization, the line clock
needed to be extracted for the internal synchronization, the jitter attenu-
ator is set in the receive path. Another use of the jitter attenuator is to
provide clock smoothing in the transmit path for applications such as
synchronous/asynchronous demultiplexing applications. In these appli-
cations, TCLK will have an instantaneous frequency that is higher than
the nominal T1/E1 data rate and in order to set the average long-term
TCLK frequency within the transmit line rate specifications, periods of
TCLK are suppressed (gapped).
The jitter attenuator integrates a FIFO which can accommodate a
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64
X 2 bits. The FIFO length determines the maximum permissible gap
width (see Table-10 Gap Width Limitation). Exceeding these values will
cause FIFO overflow or underflow. The data is 16 or 32 bits’ delay
through the jitter attenuator in the corresponding transmit or receive
path. The constant delay feature is crucial for the applications requiring
“hitless” switching.
In host mode, bit JABW in GCF determines the jitter attenuator 3 dB
corner frequency (fc) for both T1 and E1. In hardware mode, the fc is
fixed to 2.5 Hz for T1 or 1.7 Hz for E1. Generally, the lower the fc is, the
higher the attenuation. However, lower fc comes at the expense of
increased acquisition time. Therefore, the optimum fc is to optimize both
the attenuation and the acquisition time. In addition, the longer FIFO
length results in an increased throughput delay and also influences the 3
dB corner frequency. Generally, it’s recommended to use the lower
corner frequency and the shortest FIFO length that can still meet jitter
attenuation requirements.
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0
250
500
750
1000
1250
Time (ns)
Normaliz
ed
Amplit
ude
-300
-200
-100
0
100
200
300
Time (ns)
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Nor
m
al
iz
ed
A
m
pli
tude
Table-9 Built-in Waveform Template Selection
TS2
TS1
TS0
Service
Clock Rate
Cable Length
Maximum Cable Loss (dB)(1)
1. Maximum cable loss at 772 kHz.
0
E1
2.048 MHz
120
/75 Cable
-
00
1
Reserved
01
0
01
1
T1
1.544 MHz
0-133 ft. ABAM
0.6
1
0
133-266 ft. ABAM
1.2
1
0
1
266-399 ft. ABAM
1.8
1
0
399-533 ft. ABAM
2.4
1
533-655 ft. ABAM
3.0
Table-10 Gap Width Limitation
FIFO Length
Max. Gap Width
64 bit
56 UI
32 bit
28 UI
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V2048DA | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2048DAG | 功能描述:IC LIU T1/E1 8CH SHORT 144-TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2048E | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2048EBB | 功能描述:IC LIU T1/E1 8CH SHORT 208-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2048EBBG | 功能描述:IC LINE INTERFACE UNIT 208-PBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:2,500 系列:- 类型:驱动器 驱动器/接收器数:4/0 规程:RS422 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC N 包装:带卷 (TR) |
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