参数资料
型号: IDT82V2084PFG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 42/75页
文件大小: 0K
描述: IC LINE INTERFC UNIT 4CH 128TQFP
标准包装: 1
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 标准包装
其它名称: 800-1864-6
47
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-48 INTES: Interrupt Trigger Edges Select Register
(R/W, Address = 13H, 53H,93H,D3H)
Symbol
Bit
Default
Description
EQ_IES
7
0
This bit determines the Equalizer out of range interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the EQ_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the EQ_S bit in the STAT0
status register.
IBLBA_IES
6
0
This bit determines the Inband Loopback Activate Code interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the IBLBA_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in the STAT0
status register.
IBLBD_IES
5
0
This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the IBLBD_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in the STAT0
status register.
PRBS_IES
4
0
This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the PRBS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in the STAT0
status register.
TCLK_IES
3
0
This bit determines the TCLK Loss interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in the
STAT0 status register.
DF_IES
2
0
This bit determines the Driver Failure interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the DF_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in the STAT0
status register.
AIS_IES
1
0
This bit determines the AIS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the AIS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in the STAT0
status register.
LOS_IES
0
This bit determines the LOS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the LOS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in the STAT0
status register.
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