参数资料
型号: IDT82V2084PFG8
厂商: IDT, Integrated Device Technology Inc
文件页数: 43/75页
文件大小: 0K
描述: IC LINE INTERFC UNIT 4CH 128TQFP
标准包装: 1
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 标准包装
其它名称: 800-1864-6
48
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.7
LINE STATUS REGISTERS
Table-49 STAT0: Line Status Register 0 (real time status monitor)
(R, Address = 14H,54H,94H,D4H)
Symbol
Bit
Default
Description
EQ_S
7
0
Equalizer status indication
= 0: In range
= 1: out of range
IBLBA_S
6
0
Inband Loopback activate code receive status indication
= 0: no Inband Loopback activate code is detected
= 1: activate code has been detected for more than t ms. Even there is bit error, this bit remains set as long as the
bit error rate is less than 10-2.
Note1:
Automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms. If automatic remote loopback switching is
enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit activates the remote loopback operation in local end.
Note2:
If IBLBA_IM=0 and IBLBA_IES=0, a ‘0’ to ‘1’ transition on this bit will cause an activate code detect interrupt.
If IBLBA_IM=0 and IBLBA_IES=1, any changes on this bit will cause an activate code detect interrupt.
IBLBD_S
5
0
Inband Loopback deactivate code receive status indication
= 0: no Inband Loopback deactivate code is detected
= 1: the Inband Loopback deactivate code has been detected for more than t. Even there is a bit error, this bit
remains set as long as the bit error rate is less than 10-2.
Note1:
Automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.If automatic remote loopback switching is
enabled (ARLP = 1), t= 5.1 s. The rising edge of this bit disables the remote loopback operation.
Note2:
If IBLBD_IM=0 and IBLBD_IES=0, a ‘0’ to ‘1’ transition on this bit will cause a deactivate code detect interrupt.
If IBLBD_IM=0 and IBLBD_IES=1, any changes on this bit will cause a deactivate code detect interrupt.
PRBS_S
4
0
Synchronous status indication of PRBS/QRSS (real time)
= 0: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS is not detected
= 1: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS is detected.
Note:
If PRBS_IM=0 and PRBS_IES=0, a ‘0’ to ‘1’ transition on this bit will cause a synchronous status detect interrupt.
If PRBS_IM=0 and PRBS_IES=1, any changes on this bit will cause a synchronous status detect interrupt.
TCLK_LOS
3
0
TCLKn loss indication
= 0: normal
= 1: TCLKn pin has not toggled for more than 70 MCLK cycles.
Note:
If TCLK_IM=0 and TCLK_IES=0, a ‘0’ to ‘1’ transition on this bit will cause an interrupt.
If TCLK_IM=0 and TCLK_IES=1, any changes on this bit will cause an interrupt.
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