参数资料
型号: IDT82V3355TFG
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/135页
文件大小: 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
标准包装: 1
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH,Stratum
输入: CMOS,LVDS,PECL
输出: CMOS,LVDS,PECL
电路数: 1
比率 - 输入:输出: 3:2
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-TQFP(10x10)
包装: 托盘
其它名称: 82V3355TFG
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
108
May 19, 2009
6.2.9
PBO & PHASE OFFSET CONTROL REGISTERS
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1
Address:78H
Type: Read / Write
Default Value: 0X000110
Bit
Name
Description
7
IN_NOISE_WINDOW
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be
selected for T0/T4 DPLL.
0: Disabled. (default)
1: Enabled.
6-
Reserved.
5PH_MON_EN
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
is enabled to monitor the phase-time changes on the T0 selected input clock.
0: Disabled. (default)
1: Enabled.
4
PH_MON_PBO_EN
This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
3 - 0
PH_TR_MON_LIMT[3:0]
These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.
Address:7AH
Type: Read / Write
Default Value: 00000000
Bit
Name
Description
7 - 0
PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH).
76543210
IN_NOISE_WIN
DOW
-
PH_MON_EN
PH_MON_PBO
_EN
PH_TR_MON_L
IMT3
PH_TR_MON_L
IMT2
PH_TR_MON_L
IMT1
PH_TR_MON_L
IMT0
76543210
PH_OFFSET7
PH_OFFSET6
PH_OFFSET5
PH_OFFSET4
PH_OFFSET3
PH_OFFSET2
PH_OFFSET1
PH_OFFSET0
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