收藏本站
参数资料
型号： IDT82V3355TFG
厂商： IDT, Integrated Device Technology Inc
文件页数： 53/135页
文件大小： 0K
描述： IC PLL WAN SYNC ETH 64-TQFP
标准包装： 1
类型： 时钟/频率发生器，多路复用器
PLL： 是
主要目的： 以太网，SONET/SDH，Stratum
输入： CMOS，LVDS，PECL
输出： CMOS，LVDS，PECL
电路数： 1
比率 - 输入:输出： 3:2
差分 - 输入:输出： 是/是
频率 - 最大： 622.08MHz
电源电压： 3 V ~ 3.6 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-TQFP（10x10）
包装： 托盘
其它名称： 82V3355TFG
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
24
May 19, 2009
3.7
SELECTED INPUT CLOCK MONITORING
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1
T0 / T4 DPLL LOCKING DETECTION
The following events is always monitored:
Fast Loss;
Coarse Phase Loss;
Fine Phase Loss;
Hard Limit Exceeding.
3.7.1.1
Fast Loss
A fast loss is triggered when the selected input clock misses 2 con-
secutive clock cycles. It is cleared once an active clock edge is detected.
For T0 path, the occurrence of the fast loss will result in T0 DPLL
unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of
the fast loss will result in T4 DPLL unlocked regardless of the
FAST_LOS_SW bit.
3.7.1.2
Coarse Phase Loss
The T0/T4 DPLL compares the selected input clock with the feed-
back signal. If the phase-compared result exceeds the coarse phase
limit, a coarse phase loss is triggered. It is cleared once the phase-com-
pared result is within the coarse phase limit.
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 11. When the selected input clock is of other frequencies but 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 12.
The occurrence of the coarse phase loss will result in T0/T4 DPLL
unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.3
Fine Phase Loss
The T0/T4 DPLL compares the selected input clock with the feed-
back signal. If the phase-compared result exceeds the fine phase limit
programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
The occurrence of the fine phase loss will result in T0/T4 DPLL
unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is
indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM /
T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard
alarm will result in T0/T4 DPLL unlocked if the FREQ_LIMT_PH_LOS bit
is ‘1’.
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2
LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
Fast Loss (the FAST_LOS_SW bit is ‘1’);
Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
The DPLL locking status is indicated by the T0_DPLL_LOCK /
T4_DPLL_LOCK bit.
The T4_STS 1 bit will be set when the locking status of the T4 DPLL
changes (from ‘lock’ to ‘unlock’ or from ‘unlock’ to ‘lock’). If the T4_STS 2
bit is ‘1’, an interrupt will be generated.
Table 11: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
MULTI_PH_8K_4K
_2K_EN
WIDE_EN
Coarse Phase Limit
0
don’t-care
±1 UI
1
0±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
Table 12: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
WIDE_EN
Coarse Phase Limit
0±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
相关PDF资料
PDF描述
D38999/26SF11PA CONN PLUG 11POS STRAIGHT W/PINS
VE-B2V-MW-F4 CONVERTER MOD DC/DC 5.8V 100W
VE-B2T-MW-F1 CONVERTER MOD DC/DC 6.5V 100W
D38999/26MH21SA CONN PLUG 21POS STRAIGHT W/SCKT
MS3450L18-9S CONN RCPT 7POS WALL MNT W/SCKT
相关代理商/技术参数
参数描述
IDT82V3355TFG8 功能描述:IC PLL WAN SYNC ETH 64-TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3355TFGBLANK 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL
IDT82V3358 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL
IDT82V3358EDG 功能描述:IC PLL WAN SYNC ETHERNET 64TQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT
IDT82V3358EDG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SYNC ETHERNET 64TQFP
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*