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| 型号： | IDT8737-11PGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8737 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 1/12页 |
| 文件大小： | 98K |
| 代理商： | IDT8737-11PGI8 |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT8737-11
LOW SKEW,
÷÷÷÷÷1/÷÷÷÷÷2 DIFFERENTIAL-TO-3.3V LVPECL
AUGUST 2004
2004
Integrated Device Technology, Inc.
DSC 6168/5
c
IDT8737-11
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW,
÷÷÷÷÷1/÷÷÷÷÷2
DIFFERENTIAL-TO-3.3V
LVPECL FANOUT BUFFER
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Two divide-by-1 and two divide-by-2 differential 3.3V LVPECL
outputs
Selectable differential CLK, xCLK, or LVPECL clock inputs
CLK, xCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, and HCSL
PCLK, xPCLK supports the following input types: LVPECL, CML,
and SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signal (LVCMOS, LVTTL, GTL)
to LVPECL levels with resistor bias on xCLK input
Output skew: 60ps (max.)
Part-to-part skew: as low as 200ps
Bank skew:
- Bank A, as low as 20ps
- Bank B, as low as 35ps
Propagation delay: 1.7ns (max.)
3.3V operating supply
Available in TSSOP package
DESCRIPTION:
The IDT8737-11 is a low skew, high performance differential-to-3.3V
LVPECL fanout buffer-divider. It has two selectable clock inputs. The CLK/
xCLK pair can accept most standard differential input levels. The PCLK/
xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable
is internally synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteedoutputandpart-to-partskewcharacteristicsmaketheIDT8737-
11 ideal for clock distribution applications that demand well-defined perfor-
mance and repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
CLK
xCLK
PCLK
xPCLK
CLK_SEL
MR
0
1
D
LE
Q
÷1
÷2
QA0
xQA0
QA1
xQA1
QB0
xQB0
QB1
xQB1
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