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| 型号： | IDT8737-11PGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8737 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 6/12页 |
| 文件大小： | 98K |
| 代理商： | IDT8737-11PGI8 |
3
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT8737-11
LOW SKEW,
÷÷÷÷÷1/÷÷÷÷÷2 DIFFERENTIAL-TO-3.3V LVPECL
CONTROL INPUT FUNCTION TABLE(1,2)
Inputs
Outputs
MR
CLK_EN
CLK_SEL
Selected Source
QA0, QA1
xQA0, xQA1
QB0, QB1
xQB0, xQB1
1
X
LOW
HIGH
LOW
HIGH
0
CLK, xCLK
Disabled; LOW
Disabled; HIGH
Disabled; LOW
Disabled; HIGH
0
1
PCLK, xPCLK
Disabled; LOW
Disabled; HIGH
Disabled; LOW
Disabled; HIGH
0
1
0
CLK, xCLK
Enabled
0
1
PCLK, xPCLK
Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
CLOCK INPUT FUNCTION TABLE(1)
Inputs
Outputs
CLK or PCLK
xCLK or xPCLK
QAx
xQAx
QBx
xQBx
Input to Output Mode
Polarity
0
1
L
H
L
H
DifferentialtoDifferential
Non-Inverting
1
0
H
L
H
L
DifferentialtoDifferential
Non-Inverting
0
Biased(2)
L
H
L
H
Single-EndedtoDifferential
Non-Inverting
1
Biased(2)
H
L
H
L
Single-EndedtoDifferential
Non-Inverting
Biased(2)
1
L
H
L
H
Single-EndedtoDifferential
Inverting
Biased(2)
0
H
L
H
L
Single-EndedtoDifferential
Inverting
NOTES:
1. H = HIGH
L = LOW
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
CLK_EN
CLK, PCLK
xCLK, xPCLK
QA0, QA1,
QB0, QB1
xQA0, xQA1,
xQB0, xQB1
≈
Disabled
Enabled
≈
CLK_EN Timing Diagram
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