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参数资料
| 型号： | IDT8737-11PGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 8737 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 5/12页 |
| 文件大小： | 98K |
| 代理商： | IDT8737-11PGI8 |
2
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT8737-11
LOW SKEW,
÷÷÷÷÷1/÷÷÷÷÷2 DIFFERENTIAL-TO-3.3V LVPECL
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VDD
Power Supply Voltage
4.6
V
VI
Input Voltage
–0.5 to VDD+0.5
V
VO
Output Voltage
–0.5 to VDD+0.5
V
θJA
Package Thermal Impedance (0 lfpm)
92.6
°C/W
TSTG
Storage Temperature
–65 to +150
° C
CAPACITANCE(TA=+25°C,f=1MHz,V
IN
= 0V)
Parameter
Description
Typ.
Max.
Unit
CIN
InputCapacitance
—
4
pF
RPULLUP
Input Pullup Resistor
51
—
K
Ω
RPULLDOWN
Input Pulldown Resistor
51
—
K
Ω
TSSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VEE
CLK_EN
CLK_SEL
CLK
xCLK
PCLK
xPCLK
NC
MR
VDD
QA0
xQA0
VDD
QA1
xQA1
QB0
xQB0
VDD
QB1
xQB1
PIN DESCRIPTION(1)
Symbol
Number
Type
Description
VEE
1
Power
Negative Supply Pin
CLK_EN
2
Input
Pullup
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
CLK_SEL
3
Input
Pulldown
Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects
CLK / xCLK inputs. LVTTL / LVCMOS interface levels.
CLK
4
Input
Pulldown
Non-Inverting Differential Clock Input
xCLK
5
Input
Pullup
Inverting Differential Clock Input
PCLK
6
Input
Pulldown
Non-Inverting Differential LVPECL Clock Input
xPCLK
7
Input
Pullup
Inverting Differential LVPECL Clock Input
N C
8
Unused
No Connection
MR
9
Input
Pulldown
Master Reset. Resets the output divider. LVTTL / LVCMOS interface levels.
VDD
10, 13, 18
Power
Positive Supply Pins
xQB1, QB1
11, 12
Output
Differential Output Pair. LVTTL / LVCMOS interface levels.
xQB0, QB0
14, 15
Output
Differential Output Pair. LVTTL / LVCMOS interface levels.
xQA1, QA1
16, 17
Output
Differential Output Pair. LVTTL / LVCMOS interface levels.
xQA0, QA0
19, 20
Output
Differential Output Pair. LVTTL / LVCMOS interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
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