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参数资料
| 型号： | IN74LV574N |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal D-type flip-flop; positive edge-trigger (3-State) |
| 中文描述： | 八路D型触发器;上升沿触发（3态） |
| 文件页数： | 4/8页 |
| 文件大小： | 194K |
| 代理商： | IN74LV574N |
IN74LV574
4
INTEGRAL
I
OZ
Three state
leakage
current
3-state output
V
I
(11) = V
IH
V
O
=V
CC
or 0 V
5.5
-
±
0.5
-
±
0.5
-
±
5
-
±
10
μ
à
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
Test
V
CC
Guaranteed Limit
85
°
C
Symbol
Parameter
conditions
V
-40
°
C to
25
°
C
125
°
C
Unit
min
max
min
max
min
max
t
PHL,
t
PLH
Propagation delay , Clock
to Q
V
I
= 0 V or V
1
Figures 1,3
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
26
20
16
14
-
-
-
-
-
170
34
25
20
17
-
-
-
-
-
200
43
31
25
21
ns
t
PHZ,
t
PLZ
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
160
31
23
20
17
-
-
-
-
-
170
39
29
24
20
-
-
-
-
-
200
48
36
29
24
ns
t
PZH,
t
PZL
Propagation delay, OE to
Q
V
I
= 0 V or V
1
Figures 2,4
1.2
2.0
2.7
3.0
4.5
-
-
-
-
-
140
26
20
16
14
-
-
-
-
-
160
34
25
20
17
-
-
-
-
-
180
43
31
25
21
ns
C
I
Input capacitance
5.5
-
7.0*
-
-
-
-
pF
C
PD
Power dissipation
capacitance (per flip-flop)
V
I
= 0 V or V
CC
5.5
-
50*
-
-
-
-
pF
* T = 25
o
C
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 1. Test Circuit
Figure 2. Test Circuit
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=2.5 ns)
DEVICE
UNDER
TEST
OUTPUT
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1 k
C
L
*
TEST POINT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND
when
testing t
PHZ
and t
PZH
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