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参数资料
| 型号： | IN74LV574N |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal D-type flip-flop; positive edge-trigger (3-State) |
| 中文描述： | 八路D型触发器;上升沿触发（3态） |
| 文件页数： | 8/8页 |
| 文件大小： | 194K |
| 代理商： | IN74LV574N |
IN74LV574
8
INTEGRAL
Location of marking (mm):
left lower corner x=1.656, y=1.353.
Chip thickness:
0.46
±
0.02 mm, (0.35
±
0.02 mm – for SOIC).
PAD LOCATION
Location (left lower corner), mm
X
0.128
0.128
0.330
0.576
0.738
1.054
1.216
1.466
1.682
1.682
1.682
1.682
1.422
1.149
0.971
0.811
0.633
0.360
0.128
0.128
Pad No
Symbol
Y
Pad size, mm
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
Output enable
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
GND
Clock
Q 7
Q 6
Q 5
Q 4
Q 3
Q 2
Q 1
Q 0
V
CC
0.545
0.229
0.120
0.120
0.120
0.120
0.120
0.120
0.314
0.533
0.839
1.108
1.274
1.274
1.274
1.274
1.274
1.274
1.108
0.854
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
Note: Pad location is given as per metallization layer
01
10
02
X
Y
11
20
19
03
(0,0)
12
04
13
05
1.9 + 0.03
1
14
Chip marking
êáLV574
06
15
07
16
08
17
09
18
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|---|---|
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| IN74LV640N | Octal 3-State Inverting Bus Transceiver |
| IN74LV74 | Dual D-type flip-flop with set and reset; positive-edge trigger |
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