参数资料
型号: IP1203TR
厂商: International Rectifier
文件页数: 19/23页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 15A 24LGA
产品变化通告: (EP) Parts Discontinuation 25/May/2012
标准包装: 1,000
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 8 V
输入电压: 5.5 V ~ 13.2 V
频率 - 开关: 200kHz ~ 400kHz
电流 - 输出: 15A
同步整流器:
工作温度: -10°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-LGA
包装: 带卷 (TR)
供应商设备封装: LGA(9x9)
配用: IRDCIP1203-A-ND - IP1203 REFERENCE DESIGN KIT
iP1203
Layout Guidelines
For stable and noise free operation of the whole
power system, it is recommended that the design-
ers use the following guidelines:
1. Follow the layout scheme presented in Fig. 23.
Make sure that the output inductor L is placed as
close to iP1203 as possible to prevent noise propa-
gation that can be caused by switching of power at
the switching node Vsw, to sensitive circuits.
2. Provide a mid-layer solid ground plane with con-
nections to the top layer through vias. The PGND
pads of iP1203 also need to be connected to the
same ground plane through vias.
3. To increase power supply noise immunity, place
input and output capacitors close to one another,
as shown in the layout diagram. This will provide
short high current paths that are essential at the
ground terminals.
4. Although there is a certain degree of V IN bypass-
ing inside the iP1203, the external input decoupling
capacitors should be as close to the device as pos-
sible.
5. The feedback track from the output V OUT to FB
should be routed as far away from noise generating
traces as possible.
6. The compensation components and the Vref by-
pass capacitor should be placed as close as pos-
sible to their corresponding iP1203 pins, away from
noise generating traces.
7. Refer to IR application note AN-1029 (Optimizing
a PCB Layout for an iPOWIR Technology Design) to
determine what size vias and copper weight and
thickness to use when designing the PCB.
8. Place the overcurrent threshold setting resistors
R OCSET close to the iP1203 block at the correspond-
ing connection node.
www.irf.com
Fig. 23: iP1203 Suggested Layout
19
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