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参数资料
| 型号： | IP82C88 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 外设及接口 |
| 英文描述： | CMOS Bus Controller |
| 中文描述： | 8 MHz, CONTROL AND CMD SIG GEN, PDIP20 |
| 文件页数： | 4/10页 |
| 文件大小： | 129K |
| 代理商： | IP82C88 |
4-336
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
Control Outputs
The control outputs of the 82C88 are Data Enable (DEN),
Data Transmit/Receive (DT/R) and Master Cascade Enable/
Peripheral Data Enable (MCE/PDEN). The DEN signal
determines when the external bus should be enabled onto
the local bus and the DT/R determines the direction of data
transfer. These two signals usually go to the chip select and
direction pins of a transceiver.
The MCE/PDEN pin changes function with the two modes of
the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),
the PDEN signal serves as a dedicated data enable signal
for the I/O or Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the 82C88 is in the System Bus mode (IOB LOW).
During any interrupt sequence, there are two interrupt
acknowledge cycles that occur back to back. During the first
interrupt cycle no data or address transfers take place. Logic
should be provided to mask off MCE during this cycle. Just
before the second cycle begins the MCE signal gates a mas-
ter Priority Interrupt Controller’s (PIC) cascade address onto
the processor’s local bus where ALE (Address Latch Enable)
strobes it into the address latches. On the leading edge of
the second interrupt cycle, the addressed slave PIC gates an
interrupt vector onto the system data bus where it is read by
the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82/82C83H address latches. ALE also serves to strobe
the status (S0, S1, S2) into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
functions normally. If the CEN pin is pulled LOW, all com-
mand lines are held in their inactive state (not three-state).
This feature can be used to implement memory partitioning
and to eliminate address conflicts between system bus
devices and resident bus devices.
82C88
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