参数资料
| 型号： | IPR-ED8B10B |
| 厂商： | Altera |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IP 8B10B ENCODER/DECODER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 编码器/解码器，8b/10b 用于千兆位以太网和光纤通道 |
| 许可证： | 续用许可证 |
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
CASCADED DECODING
Two decoders can be cascaded to decode two words simultaneously. The
decoders are cascaded—in a similar fashion as the encoders—by
connecting the rdcascade output of the first decoder to the rdin input
of the second decoder, and by connecting the rdout output of the second
decoder to the rdin input of the first decoder. The rdforce inputs of
both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the rdin and
rdforce inputs are not cascaded. If these inputs are to be used in non-
cascaded decoders, they should be delayed by one clock cycle with respect
to their corresponding datain and kin inputs.
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to
be decoded. The decoded value—corresponding to the value of datain
sampled by the decoder on rising edge n —is output shortly after rising
edge n+1 , and is available to be sampled on the rising edge of clock cycle
n+2 . (See Figure 4 on page 7 ).
Figure 6. Decoder Timing Diagram
n
n+1
n+2
n+3
clk
datain,
a
b
c
d
e
f
g
enable
dataout,
kout, kerr,
a
b
c
d
e
rdout, rderr
rdforce,
a
b
c
d
e
f
rdin
8
Altera Corporation
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