参数资料
| 型号： | IPR-ED8B10B |
| 厂商： | Altera |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IP 8B10B ENCODER/DECODER RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | 编码器/解码器，8b/10b 用于千兆位以太网和光纤通道 |
| 许可证： | 续用许可证 |
8b10b Encoder/Decoder MegaCore Function (ED8B10B) Data Sheet
I/O Signals
Table 2. Encoder I/O Signals
Signal Name
clk
reset_n
kin
enable
idle_ins
datain[7:0]
rdin
rdforce
kerr
dataout[9:0]
valid
rdout
rdcascade
Direction
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Description
Clock. The input is latched, and the result is output on this clock. There
is a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Command byte indicator. When high, indicates that the input is a
command byte, not a data byte.
Enable encoder signal. When high, indicates that the data currently
present on the datain input is to be encoded.
Idle character insert. When high, idle (K28.5) characters are inserted
when enable is not asserted.
Data input. This is the 8-bit input word, data or command.
Running disparity input. When rdforce is high, the value on this pin is
used as the current running disparity instead of the internally generated
one.
Force running disparity. When high, the rdin value overrides the
internally generated running disparity.
Special K character error. This signal is set high when enable and kin
are high and the value on datain is not a valid special K character.
Data output. This is the 10-bit encoded output.
Valid signal. When high, indicates that a valid encoded word is present
on the dataout output.
Running disparity output. The current running disparity (after encoding
the word present on the dataout output).
Cascaded Running disparity. Used when encoders are cascaded.
Table 3. Decoder I/O Signals
Signal Name
clk
reset_n
idle_del
enable
datain[9:0]
Altera Corporation
Direction
Input
Input
Input
Input
Input
Description
Clock. The input is latched, and the result output on this clock. There is
a three clock cycle latency between the input and output.
Active low, reset. Asynchronously resets all registers in the core.
Idle delete signal. When high, idle words (K28.5) are removed from the
stream (i.e. valid is set low when idle words are received).
Enable decoder signal. When high, indicates that the data currently
present on the datain input is to be decoded.
Data input. This is the 10-bit encoded input word.
9
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