- 您现在的位置：买卖IC网 > PDF目录79605 > IQ80C154-12R (ATMEL CORP) 8-BIT, 12 MHz, MICROCONTROLLER, CQFP44 PDF资料下载
参数资料
| 型号： | IQ80C154-12R |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CQFP44 |
| 封装： | CERAMIC, QFP-44 |
| 文件页数： | 26/109页 |
| 文件大小： | 10824K |
| 代理商： | IQ80C154-12R |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页当前第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页
271
7593L–AVR–09/12
AT90USB64/128
If the endpoint uses two banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
23.14.2.1
Abort
An “abort” stage can be produced by the host in some situations:
In a control transaction: ZLP data OUT received during a IN stage
In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 23-1.
Abort flow.
23.15 Isochronous mode
23.15.1
Underflow
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
23.15.2
CRC error
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt
from being triggered.
Endpoint
Abort
Abort done
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Disable the TXINI interrupt.
Endpoint
reset
NBUSYBK
=0
Yes
Clear
UEIENX.
TXINE
No
KILLBK=1
Yes
Kill the last written
bank.
Wait for the end of the
procedure.
No
相关PDF资料 |
PDF描述 |
|---|---|
| IF183C154XXX-12R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| IT83C154DCXXX-12R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| IF183C154CXXX-L16 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| IQ83C154CXXX-16 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| IF283C154DTXXX-L16D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IQ80C154-16 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| IQ80C154-20 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| IQ80C154-25 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| IQ80C154-30 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| IQ80C154-36 | 制造商:TEMIC 制造商全称:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
发布紧急采购，3分钟左右您将得到回复。