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| 型号： | IR2114SS |
| 厂商： | International Rectifier |
| 文件页数： | 20/33页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER HALF-BRIDGE 24-SSOP |
| 标准包装： | 55 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 440ns |
| 电流 - 峰： | 2A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 600V |
| 电源电压： | 11.5 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
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IR2114/IR2214SSPbF
3 PCB Layout Tips
3.5 Routing and Placement Example
3.1 Distance from High to Low Voltage
The IR2x14x pinout maximizes the distance between
floating (from DC- to DC+) and low voltage pins. It’s
strongly recommended to place components tied to
floating voltage on the high voltage side of device (V B ,
V S side) while the other components are placed on the
opposite side.
3.2 Ground Plane
To minimize noise coupling, the ground plane must not
be placed under or near the high voltage floating side.
Figure 24 shows one of the possible layout solutions
using a 3 layer PCB. This example takes into account
all the previous considerations. Placement and routing
for supply capacitors and gate resistances in the high
and low voltage side minimize the supply path loop and
the gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible to
the bootstrap capacitor and the anode far from high
voltage and close to V CC .
3.3 Gate Drive Loops
V GH
R2
R3
D2
DC+
Current loops behave like antennas and are able to
R4
receive and transmit EM noise. In order to reduce the
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
V GL
R5
IR2214
D3
Phase
much as possible. Figure 23 shows the high and low
side gate loops.
Moreover, current can be injected inside the gate drive
loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate
loop contributes to developing a voltage across the
gate-emitter, increasing the possibility of self turn-on.
For this reason, it is strongly recommended to place the
three gate resistances close together and to minimize
the loop area (see Fig. 23).
I GC
VB/ VCC
gate
V EH
V EL
R6
R7
V CC
R1
a)
C2
Top Layer
C1
H/LOP
H/LON
SSDH/L
resistance
Gate Drive
Loop
V GE
C GC
b) Bottom Layer
VS/COM
Figure 23: gate drive loop
3.4 Supply Capacitors
The IR2x14x output stages are able to quickly turn on
an IGBT, with up to 2 A of output current. The supply
capacitors must be placed as close as possible to the
device pins (V CC and V SS for the ground tied supply, V B
and V S for the floating supply) in order to minimize
parasitic inductance/resistance.
www.irf.com
20
c) Ground Plane
Figure 24: layout example
Information below refers to Fig. 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
? 2009 International Rectifier
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