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| 型号： | IR21381QPBF |
| 厂商： | International Rectifier |
| 文件页数： | 27/30页 |
| 文件大小： | 0K |
| 描述： | IC CTLR AC MOTOR 3PHASE 64-MQFP |
| 标准包装： | 660 |
| 配置： | 3 相桥 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 550ns |
| 电流 - 峰： | 350mA |
| 配置数： | 1 |
| 输出数： | 3 |
| 高端电压 - 最大（自引导启动）： | 600V |
| 电源电压： | 12.5 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-MQFP，64-PQFP |
| 供应商设备封装： | 64-MQFP（20x14） |
| 包装： | 带卷 (TR) |
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IR22381Q PBF /IR21381Q ( P b F )
Table 3: RGoff sizing
IGBT
Vth(min)
CRESoff
RGoff
GB15XP120K* 5
GB05XP120K 5
IRG4PH20K(D) 5
* sized with 18V supply
38pF
12pF
11pF
RGoff = 0 ?
RGoff ≤ 55 ?
RGoff ≤ 63 ?
3
PCB LAYOUT TIPS
3.1
Distance from H to L voltage
The IR22381/IR21381Q pin out lacks some pins
(see Figure 17) maximizing the distance between
floating (from DC- to DC+) and low voltage pins . It’s
strongly recommended to place components tied to
floating voltage in the respective high voltage
portions of the device (VB 1,2,3 , VS 1,2,3 ) side.
Figure 27: gate drive loop
3.2
Ground plane
Ground plane must not be placed under or nearby
the high voltage floating side to minimize noise
3.4
Supply capacitors
coupling.
3.3 Gate drive loops
Current loops behave like an antenna able to
receive and transmit EM noise. In order to reduce
EM coupling and improve the power switch turn
on/off performances, gate drive loops must be
IR22381 output stages are able to quickly turn on
IGBT with up to 460mA of output current. The
supply capacitors must be placed as close as
possible to the device pins (V CC and V SS for the
ground tied supply, V B and V S for the floating
supply) in order to minimize parasitic
inductance/resistance.
reduced as much as possible. Figure 23 shows the
high and low side gate loops.
Moreover, current can be injected inside the gate
3.5
Routing and placement
example
drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the
gate loop contributes to develop a voltage across
the gate-emitter increasing the possibility of self
turn-on effect. For this reason is strongly
recommended to place the three gate resistances
close together and to minimize the loop area (see
Figure 27).
27
Figure 28 shows one of the possible layout
solutions using a 3 layer PCB (low voltage signals
not shown) on an ECONO PIM module. This
example takes into account all the previous
considerations. Placement and routing for supply
capacitors and gate resistances in the high and low
voltage side minimize respectively supply path and
gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible
to bootstrap capacitor and the anode far from high
voltage and close to V CC .
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