参数资料
型号: IR3092M
厂商: International Rectifier
文件页数: 21/37页
文件大小: 0K
描述: IC CONTROLLER 2PHASE 48-MLPQ
标准包装: 100
应用: VID 电压编程器
电源电压: 7.3 V ~ 21 V
电流 - 电源: 29mA
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 48-MLPQ
供应商设备封装: 48-MLPQ(7x7)
包装: 剪切带 (CT)
其它名称: *IR3092M
IR3092
Adaptive Voltage Positioning
Adaptive voltage positioning is needed to reduce output voltage deviations during load transients and power dissipation of
the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in Figure 9. Resistor
R FB is connected between the Error Amplifier’s inverting input pin FB and the converter’s output voltage. An internal
current source whose value is programmed by the same external resistor that programs the oscillator frequency, R ROSC ,
pumps current out of the FB pin. The FB bias current develops a positioning voltage drop across R FB which forces the
converter’s output voltage lower to V(VDAC)-I(FB)* R FB to maintain a balance at the Error Amplifier inputs. R FB is
selected to program the desired amount of fixed offset voltage below the DAC voltage.
The voltage at the VDRP pin is an average of both phase Current Sense Amplifiers and represents the sum of the VDAC
voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor.
The Error Amplifier forces the voltage on the FB pin to equal VDAC through the power supply loop therefore the current
through RDRP is equal to (VDRP-VDAC) / R DRP. As the load current increases, the VDRP voltage increases accordingly
which results in an increase R FB current, further positioning the output regulated voltage lower thus making the output
voltage reduction proportional to an increase in load current. The droop impedance or output impedance of the converter
can thus be programmed by the resistor R DRP. The offset and slope of the converter output impedance are independent
of the VDAC voltage.
AMD specifies the acceptable power supply regulation window as ±50mV around their specified VID tables. VR10.X
specifies the VID table voltages as the absolute maximum power supply voltage. In order to have all three DAC options,
the OPTERON and ATHLON DAC output voltages are pre-positioned 50mV higher than listed in AMD specs. During
testing, a series resistor is placed between EAOUT and FB to cancel the additional 50mV out of the DAC. The FB bias
current, equal to IROSC, develops the 50mV cancellation voltage. Trimming the VDAC voltage by monitoring V(EAOUT)
with this 50mV cancellation resistor in circuit also trims out errors in the FB bias current.
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can be
retrieved by subtracting the VDAC voltage from the VDRP voltage.
VDAC
CDAC
RDAC
VOSNS-
FB
VDAC
ERROR AMPLIFIER
RCOMP
CCOMP
IROSC
VDAC
EAOUT
X24.5
-
CSINM3
CSINP3
VDRP
IROSC
IDRP RDRP
- V(CSavg) +
VDRP BUFFER
VDAC
X24.5
+
-
CSINM2
CSINP2
+
+
VPOSITIONING
-
VOUT SENSE+
RFB
VOUT SENSE-
Figure 9 - Adaptive voltage positioning
Page 21 of 37
06/25/04
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