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参数资料
| 型号： | IR3094MPBF |
| 厂商： | International Rectifier |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48MLPQ |
| 标准包装： | 200 |
| PWM 型： | 电压模式 |
| 输出数： | 3 |
| 频率 - 最大： | 540kHz |
| 占空比： | 100% |
| 电源电压： | 8 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 150°C |
| 封装/外壳： | 48-MLPQ |
| 包装： | 剪切带 (CT) |
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IR3094PBF
APPLICATIONS INFORMATION
OVP
ENABLE
VOUT+
VIN
RCS1
CCS1
C5VREF
CBST1
1
2
L1
RFB
RROSC
RREF
ROCSET
CREF
RDRP
RCOMP CCOMP
CSC3
CSC2
CSS
RSC3
VIN RSC2
NC
NC
ROSC
VOSNS-
OCSET
VREF
VDRP
FB
EAOUT
SS/DEL
SCOMP2
SCOMP3
Cosns-
VIN
RSET
IR3094
48LD MLPQ
GATEH1
PGND1
GATEL1
VCCL1_2
5VUVL
GATEL2
PGND2
GATEH2
VCCH2
VCCH3
GATEH3
PGND3
CBIAS
CBST3
CBST2
VIN
1
VIN
L3
1
RCS2
2
L2
2
CCS2
COUT
VOUT SENSE+
VOUT+
GND
VOUT SENSE-
CVCC
CVIN
RCS3
CCS3
GND
PGOOD
Figure 6 – System Diagram
Oscillator Resistor R ROSC
The oscillator frequency is programmable from 100kHz to 540kHz with an external resistor R ROSC as shown in
Figure 6. The Oscillator generates an internal 50% duty cycle sawtooth signal (Figure 3.) that is used to generate
120° out-of-phase timing pulses to set Phase 1,2 and 3 RS flip-flops. Once the switching frequency is chosen,
R ROSC can be determined from the curve in the Typical Operating Characteristics Section.
Soft Start, Over-Current Fault Delay, and Hiccup Mode
The IR3094 has a programmable soft-start function to limit the surge current during converter power-up. A capacitor
connected between the SS/DEL and LGND pins controls soft start timing as well as over-current protection delay
and hiccup mode timing.
Figure 8 depicts the various operating modes of the SS/DEL function. Under a no fault condition, the SS/DEL
capacitor will charge. The SS/DEL charge soft-start duration is controlled by a 60uA charge current which charges
CSS up to 4.0V. The Error Amplifier output is clamped low until SS/DEL reaches 1.1V. The Error Amplifier will then
regulate the converter’s output voltage to match the SS/DEL voltage less the 1.1V offset until it reaches the level
determined by the VREF voltage. The PWRGD signal is asserted once the SS/DEL voltage exceeds 3.75V.
Four different faults will immediately cause SS/DEL to begin discharging and set the Fault Latch once SS/DEL is
below 3.75V;
Page 15 of 29
09/26/05
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