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参数资料
| 型号： | IR3094MPBF |
| 厂商： | International Rectifier |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48MLPQ |
| 标准包装： | 200 |
| PWM 型： | 电压模式 |
| 输出数： | 3 |
| 频率 - 最大： | 540kHz |
| 占空比： | 100% |
| 电源电压： | 8 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 150°C |
| 封装/外壳： | 48-MLPQ |
| 包装： | 剪切带 (CT) |
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C SS * ' V C SS * 1 . 1
t SSDEL (4)
IR3094PBF
Once C SS is chosen, the soft start delay time t SSDEL, the over-current fault latch delay time t OCDEL , and the delay
time t VccPG from output voltage (V O ) in regulation to Power Good are fixed and shown in equation (4), (5) and (6)
respectively.
I CHG 60 * 10 6
t OCDEL
t VccPG
C SS * ' V
I DISCHG
C SS * ' V
I CHG
C SS * 0. 25
61 * 10 6
C SS * ( 3. 75 V O 1 . 1)
60 * 10 6
(5)
(6)
VREF Compensation Network R REF and C REF
A RC network tied between VREF pin and VOSENS- is needed to compensate VREF circuit. VREF should come up
earlier than SS/DEL pin charged up to 3.75V. For save estimation, use half of the soft start time that is 0.5* t SS as
the VREF voltage establishing time. Use equation (7) and (8) to determine R REF and C REF where VREF source
current I SOURCE is determained by R ROSC and can be found using the curve in the TYPICAL OPERATING
CHARACTERISTICS section.
C REF
I SOURCE * 0. 5 * t SS
V REF
(7)
C REF
R REF
0 . 5
3 . 2 10 15
2
(8)
Over Current Protection (OCP)
The current limit threshold is set by a resistor connected between the OCSET and VREF pins. If the average
Current Sense Amplifier output plus VREF voltage exceeds the OCSET voltage, the over-current protection is
triggered.
A delay is included if an over-current condition occurs after a successful soft-start sequence. This is required since
over-current conditions can occur as part of normal operation due to load transients. If an over-current fault occurs
during normal operation, the Over Current Comparator will initiate the discharge of the capacitor at SS/DEL but will
not set the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to
discharge below the 245 mV offset of the delay comparator, the Fault latch will be set pulling the Error Amplifier’s
output low inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The hiccup mode duty cycle of
over current protection is determined by the fixed 10:1 ratio of the charge to discharge current.
The inductor DC resistance R L is utilized to sense the inductor current. The current limit threshold is set by a
resistor R OCSET connected between the OCSET and VREF pins, as shown in Fig6. I LIMIT is the required over
current limit. I OCSET, the bias current of OCSET pin, is set by R ROSC and is determined by the curve in the Typical
Operating Characteristics Section. OCP need to satisfy the high temperature condition. R L_MAX and R L_ROOM are
the inductor DCR at maximum temperature T L_MAX and room temperature T_ ROOM respectively, the maximum
inductor DCR can be calculated from Equation (9)
Page 17 of 29
09/26/05
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