参数资料
型号: IR3502BMTRPBF
厂商: International Rectifier
文件页数: 17/38页
文件大小: 0K
描述: IC REG XPH INTEL VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3502BMTRPBFDKR
IR3502B
Control IC
Error
VSETPT
+
Amplifier
EAOUT
Phase IC
-
+
CSIN+
VDAC
FB
IOUT
RDRP
RFB
3k
Current
-
CSIN-
VDAC
VDAC
Sense
Amplifier
VDAC
Buffer
100k
200k
IIN
+
Thermal
+
RTCMP1
RTHERM
Comp
VDRP
-
Amplifier
-
RTCMP2
Phase IC
VN
IOUT
+
CSIN+
DAC_BUFF
RTCMP3
3k
Current
-
CSIN-
Remote
VO
VDAC
Sense
Amplifier
Sense
Amplifier
+
-
VOSEN+
VOSEN-
Figure 8 Adaptive voltage positioning with thermal compensation.
Start-up Sequence
The IR3502B has a programmable soft-start function to limit the surge current during the converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay
and hiccup mode timing. A charge current of 52.5uA and discharge current of 4uA control the up slope and down
slope of the voltage at the SS/DEL pin respectively. Figure 9 depicts start-up sequence of converter with VR 11.1
VID. If there is no fault, as the ENABLE is asserted, the SS/DEL pin will start charging. The error amplifier output
EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output
voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the 1.1V boot voltage.
The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay comparator. The VID
set inputs are then activated and VDAC pin transitions to the level determined by the VID inputs. The SS/DEL
voltage continues to increase until it rises above 3.92V and allows the PGOOD signal to be asserted. SS/DEL finally
settles at 4.0V, indicating the end of the soft start. The remote sense amplifier has a very low operating range of 50
mV in order to achieve a smooth soft start of output voltage without bump.
The VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input
immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The
PGOOD pin also drives low and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared
the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set
different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive PGOOD low. However,
the latches can only be reset by cycling VCCL power.
Page 17 of 38
V3.2
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