参数资料
型号: IR3502BMTRPBF
厂商: International Rectifier
文件页数: 26/38页
文件大小: 0K
描述: IC REG XPH INTEL VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3502BMTRPBFDKR
IR3502B
DESIGN PROCEDURES - IR3502B AND IR3507 CHIPSET
IR3502B EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3502B generates square-wave pulses to synchronize the phase ICs. The switching frequency
of the each phase converter equals the PHSOUT frequency, which is set by the external resistor R OSC according
to the curve in Figure 18. The CLKOUT frequency equals the switching frequency multiplied by the phase
number. The Rosc sets the reference current used for no load offset which is given by Figure 19 and equals:
ISETPT ?
0 .595
Rosc
(1)
Soft Start Capacitor C SS/DEL
The soft start capacitor C SS/DEL programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the converter
output voltage, as shown in Figure 9. After the ENABLE pin voltage rises above 0.85V, there is a soft-start delay
time TD1 , after which the error amplifier output is released to allow the soft start of output voltage. The soft start
time TD2 represents the time during which converter voltage rises from zero to 1.1V . The VID sample delay time
(TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID
changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from VR
reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
C SS/DEL = 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
TD 1 ?
TD 2 ?
C SS / DEL *1.4
I CHG
C SS / DEL *1.1
I CHG
?
?
C SS / DEL *1.4
52 . 5 * 10 ? 6
C SS / DEL *1.1
52 . 5 * 10 ? 6
(2)
(3)
TD 3 ?
C SS / DEL * (3 ? 1 . 4 ? 1 . 1)
I CHG
?
C SS / DEL * 0 . 7
52 . 5 * 10 ? 6
(4)
TD 4 ?
C SS / DEL * V DAC ? 1 . 1
I CHG
?
C SS / DEL * V DAC ? 1 . 1
52 . 5 * 10 ? 6
(5)
TD 5 ?
C SS / DEL * (3.92 ? 3)
I CHG
? TD 4 ?
C SS / DEL * 0.92
52 . 5 * 10 ? 6
? TD 4
(6)
Page 26 of 38
V3.2
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