参数资料
型号: IR3502BMTRPBF
厂商: International Rectifier
文件页数: 25/38页
文件大小: 0K
描述: IC REG XPH INTEL VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3502BMTRPBFDKR
IR3502B
Phase Number Determination
After a daisy chain pulse is started, the IR3502B checks the timing of the input pulse at PHSIN pin to determine the
phase number. This information is used to have symmetrical phase delay between phase switching without the
need of any external component.
Single Phase Operation
In an architecture where only a single phase is needed the switching frequency is determined by the clock
frequency.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at
least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The
crossover frequency of current share loop is approximately 8 kHz.
Fault Operation Table
The Fault Table below describes the different faults that can occur and how IR3502A would react to protect the
supply and the load from possible damage. The fault types that can occur are listed in row 1. Row 2 has the method
that a fault is cleared. The first 5 faults are latched in the UV fault latch and the VCCL power has to be recycled by
switching off the input and switching it back on for the converter to work again. The rest of the faults (except for
UVLO Vout) are latched in the SS fault latch and does not need to recycle the VCCL power in order to resume
normal operation once the fault condition clears. Most of the faults disable the error amplifier (EA) and discharge the
soft start capacitor. All the faults flag PGOOD. PGOOD returns back to high when the faults are cleared. The delay
row shows reaction time after detecting a fault condition. Delays are provided to minimize the possibility of nuisance
faults.
Fault Type
Open
Daisy
Open
Control
Loop
Open
Sense
Line
Over
Voltage
VID
Disable
VCCL
UVLO
OC Before
Start-up
OC After
Start-up
VOUT
UVLO
Fault
Clearing
Method
Error Amp
Disabled
ROSC/OVP
& IIN drive
Recycle VCCL
Yes
Resume Normal Operation when Condition Clears
No
high until
No
Yes
No
OV clears
SS/DEL
Discharge
Flags
PGood
Yes
Yes
PHSOUT
No
Delay?
32 Clock
Pulses
8
PHSOUT
Pulses
No
No
1.3us
Blank
Time
250 ns
Blank
Time
No
Pulses. Count
Programmed by
ROSC value
SS/DEL
Discharge
Threshold
No
Page 25 of 38
V3.2
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