参数资料
型号: IR3527MTRPBF
厂商: International Rectifier
文件页数: 13/20页
文件大小: 0K
描述: IC CTRL XPHASE3 DUAL 24-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 28 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-MLPQ
供应商设备封装: 24-MLPQ(4x4)
包装: 带卷 (TR)
IR3527
Over Voltage Protection (OVP)
The IR3527 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a
shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive
output voltage. As shown in Figure 7, if ISHARE pin voltage is above V(VCCL) – 0.8V, which represents over-
voltage condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low.
The OVP circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side
MOSFET, which remains ON until ISHARE drops below V(VCCL) – 0.8V when over voltage ends. The over voltage
fault is latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output
(EAIN) is pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output
voltage however an SCR or N-MOSFET could be triggered with the OVP output to prevent load damage.
OUTPUT
VOLTAGE
OVP
THRESHOLD
(VO)
VCCL-800 mV
ISHARE(IIN)
GATEH
GATEL
FAULT LATCH
(CONTROL IC)
ERROR
AMPLIFIER
INPUT
(EAIN)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER
OVP
Figure 7 - Over-voltage protection waveforms
PWM Ramp
Every time the phase IC is powered up PWM ramp magnitude is calibrated to generate a 52.5 mV/%DC (typical)
ramp for a VCC=12V. For example, for a 15% duty ratio the ramp amplitude is 787.5mV for VCC=12V. Feed-
forward control is achieved because the PWM ramp varies with VCC voltage proportionally after calibration.
Debugging Mode
If CSIN+ pin is pulled up to VCCL voltage, IR3527 enters into debugging mode. Both drivers are pulled low and
ISHARE output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change.
Page 13 of 20
V3.0
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