参数资料
型号: IR3527MTRPBF
厂商: International Rectifier
文件页数: 2/20页
文件大小: 0K
描述: IC CTRL XPHASE3 DUAL 24-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 8mA
电源电压: 8 V ~ 28 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-MLPQ
供应商设备封装: 24-MLPQ(4x4)
包装: 带卷 (TR)
IR3527
ORDERING INFORMATION
Part Number
IR3527MTRPBF
* IR3527MPBF
* Samples only
PIN DESCRIPTION
Package
24 Lead MLPQ
(4 x 4 mm body)
24 Lead MLPQ
(4 x 4 mm body)
Order Quantity
3000 per reel
100 piece strips
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN
SYMBOL
CSIN1+
EAIN
ISHARE
DACIN
PSI1
PSI2
PHSIN
PHSOUT
CLKIN
SW1
GATEH1
BOOST1
VCCL1
GATEL1
PGND
GATEL2
VCCL2
BOOST2
PIN DESCRIPTION
Phase1 current sense amplifier non-inverting input and input to debug comparator
PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN) threshold.
Output of the Current Sense Amplifiers are connected to this pin through 3k ?
resistors. Voltage on this pin is equal to approximately V(DACIN) + 16 [(V CSIN1+ –
V CSIN1- ) + (V CSIN2+ – V CSIN2- )]. Connecting all Phase IC ISHARE pins together creates
a share bus which provides an indication of the average current being supplied by all
the phases. The signal is used by the Control IC for voltage positioning, over-current
protection, and in some cases current reporting. OVP mode is initiated if the voltage
on this pin rises above V(VCCL)- 0.8V.
Reference voltage input from the Control IC. The Current Sense signal and PWM
ramps are referenced to the voltage on this pin.
Input to Phase 1 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Input to Phase 2 PSI comparator. Logic low stops the phase from switching (low =
low power state)
Phase timing clock input.
Phase timing clock output.
Clock input.
Return for Phase1 high-side driver and reference for GATEL1 non-overlap
comparator.
Phase1 High-side driver output and input to GATEL1 non-overlap comparator.
Supply for Phase1 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
Supply for Phase1 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST1 pin.
Phase1 Low-side driver output and input to GATEH1 non-overlap comparator.
Return for low side drivers and reference for GATEH non-overlap comparators.
Phase2 Low-side driver output and input to GATEH2 non-overlap comparator.
Supply for Phase2 low-side driver. Internal bootstrap synchronous PFET is
connected from this pin to the BOOST pin.
Supply for Phase2 high-side driver. Internal bootstrap synchronous PFET is
connected between this pin and the VCCL1 pin.
Page 2 of 20
V3.0
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