参数资料
型号: IR3837MTR1PBF
厂商: International Rectifier
文件页数: 23/36页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 14A PQFN17
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 1
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 14.4 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 225kHz ~ 1.65MHz
电流 - 输出: 14A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-VQFN
包装: 标准包装
供应商设备封装: 17-PQFN(5x6)
其它名称: IR3837MTR1PBFDKR
IR3837MPbF
Where:
? V o = output voltage ripple
? I L = Inductor ripple current
Since the output capacitor has a major role in the
overall performance of the converter and
determines the result of transient response,
selection of the capacitor is critical. The IR3837
can perform well with all types of capacitors.
As a rule, the capacitor must have low enough
ESR to meet output ripple and load transient
requirements.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore it is advisable to select
ceramic capacitors due to their low ESR and ESL
and small size. Seven of Taiyo Yuden’s
JMK212BJ476MG-T (47uF, 6.3V, ≈ 3m ? )
capacitors is a good choice.
It is also recommended to use a 0.1μF ceramic
capacitor at the output for high frequency
filtering.
Feedback Compensation
The IR3837 is a voltage mode controller. The
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
Fig. 18. Gain and Phase of LC filter
The IR3837 uses a voltage-type error amplifier
with high-gain (110dB) and high-bandwidth
(30MHz). The output of the amplifier is available
for DC gain control and AC phase compensation.
The error amplifier can be compensated either in
type II or type III compensation.
Local feedback with Type II compensation is
shown in Fig. 19.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. If the output capacitor’s ESR
generates a zero at 5kHz to 50kHz, the zero
generates acceptable phase margin and the
Type II compensator can be used.
The ESR zero of the output capacitor is
expressed as follows:
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed-loop transfer
F ESR ?
1
2 ? π *ESR*C o
.......... .......... ....... (17)
function with the highest 0 dB crossing frequency
and adequate phase margin (greater than 45 o ).
The output LC filter introduces a double pole,
–40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180 o
(see figure 18). The resonant frequency of the LC
filter is expressed as follows:
F LC ?
1
2 ? π L o ? C o
.......... .......... .......... .. (16)
Figure 18 shows gain and phase of the LC filter.
Since we already have 180 o phase shift from the
output filter alone, the system runs the risk of
being unstable.
Fig. 19. Type II compensation network
and its asymptotic gain plot
Rev 1.31
23
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