参数资料
型号: IR3837MTR1PBF
厂商: International Rectifier
文件页数: 26/36页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 14A PQFN17
产品培训模块: SupIRBuck? Family and POL Design Tools Overview
标准包装: 1
系列: SupIRBuck™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 14.4 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 225kHz ~ 1.65MHz
电流 - 输出: 14A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-VQFN
包装: 标准包装
供应商设备封装: 17-PQFN(5x6)
其它名称: IR3837MTR1PBFDKR
IR3837MPbF
F Z 2 ? F o
? 17.63 kHz
Select crossover frequency F 0 =100 kHz
Since F LC <F 0 <Fs/2<F ESR , Type III is selected to
place the pole and zeros.
Detailed calculation of compensation Type III :
Desired Phase Margin ? ? 70 o
1 ? sin ?
1 ? sin ?
Programming the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (R OCSet ) from the SW pin
to the OCSet pin. The resistor can be calculated
by using equation (4). This resistor (R OCSet ) must
be placed close to the IC.
The R DS(on) has a positive temperature
coefficient and it should be considered for the
worst case operation (40% increase due to
temperature has been considered in below).
F P 2 ? F o
1 ? sin ?
1 ? sin ?
? 567.1 kHz
I SET ? I L ( critical ) ?
R OCSet ? I OCSet
R DS ( on )
.......... .......... ... (33)
R DS ( on ) ? 5 . 3 m ? * 1.4 ? 7.42 m ?
Select : F Z 1 ? 0 . 5 * F Z 2 ? 8.82 kHz and
F P 3 ? 0.5 * F s ? 300 kHz
Select : C 7 ? 2.2 nF
Calculate R 3 , C 3 and C 4 :
I SET ? I o ( LIM ) ? 14 A * 1.5 ? 21 A
(50% over nominal output current )
I OCSet ? 29.54 μ A (at F s ? 600 kHz)
R OCSet ? 5 . 28 k ? Select R OCSet ? 5 . 23 k ?
The optional filter capacitor from OCSet pin to
PGnd has not been used for this design.
R 3 ?
2 π * F o * L o * C o * V osc
C 7 * V in
; R 3 ? 3 . 98 k ?
Setting the Power Good Threshold
In this design IR3837 is used in normal (non-
tracking, non-sequencing) mode, therefore the
PGood thresholds are internally set at 85% and
Select : R 3 ? 4.02 k ?
115% of Vref. At startup as soon as the internal
soft start signal reaches 2V (Figure 11), and
C 4 ?
1
2 π * F Z 1 * R 3
; C 4 ? 4 . 49 nF, Select : C 4 ? 4 . 7 nF
assuming Fb voltage follows Vref, the PGood is
asserted. As long as the voltage at the Fb pin is
between the thresholds (mentioned above),
Enable is high, and no fault happens, the PGood
C 3 ?
1
2 π * F P 3 * R 3
; C 3 ? 132 pF , Select : C 3 ? 120 pF
remains high.
The PGood is an open drain output. Hence, it is
Calculate R 10 , R 8 and R 9 :
necessary to use a pull up resistor, R PG , from
PGood pin to Vcc. The value of the pull-up
resistor must be chosen such as to limit the
R 10 ?
1
2 π * C 7 * F P 2
; R 10 ? 127.5 ? , Select : R 10 ? 127 ?
current flowing into the PGood pin to less than
5mA when the output voltage is not in regulation.
A typical value used is 10k ? .
R 8 ?
1
2 π * C 7 * F Z 2
- R 10 ; R 8 ? 3.98 k ? ,
Vref Bypass Capacitor
A bypass capacitor of about 0.1uF is required to
be placed between Vref and Gnd pins. This
Select : R 8 ? 4.02 k ?
capacitor should be placed as close as possible
to Vref pin.
R 9 ?
V ref
V o - V ref
* R 8 ; R 9 ? 2.01 k ? Select : R 9 ? 2 k ?
Rev 1.31
26
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