参数资料
型号: IRS2336DSPBF
厂商: International Rectifier
文件页数: 34/49页
文件大小: 0K
描述: IC DRIVER BRIDGE 3-PHASE 28-SOIC
标准包装: 25
配置: 3 相桥
输入类型: 差分
延迟时间: 530ns
电流 - 峰: 200mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
IRS2336x(D) Family
Routing and Placement : Power stage PCB parasitic elements can contribute to large negative voltage transients at
the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it
is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side
emitter to negative bus rail stray inductance. However, where negative V S spikes remain excessive, further steps
may be taken to reduce the spike. This includes placing a resistor (5 or less) between the V S pin and the switch
node (see Figure 36), and in some cases using a clamping diode between V SS and V S (see Figure 37). See DT04-4
at www.irf.com for more detailed information.
Figure 36: V S resistor
Figure 37: V S clamping diode
Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to
the HVIC:
?
?
VCC pin voltage = 0V AND
VS or VB pin voltage > 0
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a
current conduction path is created between VCC & VB pins, as illustrated in Fig.38 below, resulting in power loss
and possible damage to the HVIC.
Figure 38: Current conduction path between VCC and VB pin
www.irf.com
34
? 2009 International Rectifier
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