参数资料
型号: IRS2336DSTRPBF
厂商: International Rectifier
文件页数: 24/49页
文件大小: 0K
描述: IC GATE DRIVER HV 3PHASE 28-SOIC
标准包装: 1
配置: 3 相桥
输入类型: 差分
延迟时间: 530ns
电流 - 峰: 200mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 标准包装
产品目录页面: 1382 (CN2011-ZH PDF)
其它名称: IRS2336DSTRPBFDKR
IRS2336x(D) Family
Fault Reporting and Programmable Fault Clear Timer
The IRS2336xD family provides an integrated fault reporting output and an adjustable fault clear timer. There are two
situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of V CC
and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally
pulled to V SS and the fault clear timer is activated. The fault output stays in the low state until the fault condition has
been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the FAULT pin will
return to V CC .
The length of the fault clear time period (t FLTCLR ) is determined by exponential charging characteristics of the capacitor
where the time constant is set by R RCIN and C RCIN . In Figure 12 where we see that a fault condition has occurred
(UVLO or ITRIP), RCIN and FAULT are pulled to V SS , and once the fault has been removed, the fault clear timer
begins. Figure 13 shows that R RCIN is connected between the V CC and the RCIN pin, while C RCIN is placed between
the RCIN and V SS pins.
Figure 12: RCIN and FAULT pin waveforms
Figure 13: Programming the fault clear timer
The design guidelines for this network are shown in Table 3.
≤1 nF
C RCIN
Ceramic
0.5 M
to 2 M
R RCIN
>> R ON,RCIN
Table 3: Design guidelines
The length of the fault clear time period can be determined by using the formula below.
v C (t) = V f (1-e
-t/RC
)
t FLTCLR = -(R RCIN C RCIN )ln(1-V RCIN,TH /V CC )
www.irf.com
24
? 2009 International Rectifier
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