参数资料
型号: IRU3046CFTR
厂商: International Rectifier
文件页数: 12/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24TSSOP
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 450kHz
占空比: 90%
电源电压: 5 V ~ 12 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
包装: 剪切带 (CT)
产品目录页面: 1384 (CN2011-ZH PDF)
其它名称: *IRU3046CFTR
IRU3046CFCT
IRU3046
=1
H(Fo) = g m 3 R S1 3 R 2 3
V IN - V OUT
2 p3 Fo 3 L 2 3 V OSC
---(19)
LDO Power MOSFET Selection
The first step in selecting the power MOSFET for the
linear regulator is to select the maximum R DS(ON) based
From (18), R 2 can be express as:
on the input to the dropout voltage and the maximum
R 2 =
1
g m 3 R S1
3
2 p 3 F O2 3 L 2 3 V OSC
V IN(SLAVE) - V OUT
---(20)
load current.
R DS(ON) =
V IN3 - V OUT2
I OUT2
Set the zero of compensator to be half of F LC(SLAVE) , the
compensator capacitor, C 2 , can be calculated as:
For:
V IN3 = 3.3V
V OUT2 = 2.5V
F LC(SLAVE) =
2 p
1
L 2 3 C OUT
I OUT2 = 2A
Results to: R DS(ON)(MAX) = 0.4 V
Fz =
F LC(SLAVE)
2
Note that since the MOSFET R DS(ON) increases with tem-
perature, this number must be divided by ~1.5 in order
C 2 =
1
2 p 3 R 2 3 Fz
---(21)
to find the R DS(ON)(MAX) at room temperature. The IRLR2703
has a maximum of 0.065 V R DS(ON) at room temperature,
which meets our requirements.
Using equations (20) and (21) we get the following val-
ues for R 2 and C 2 .
R 2 =16.45K; Choose: R 2 =16.5K
C 2 =6606pF; Choose: C 2 =6800pF
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
LDO Section
Start to place the power components, make all the con-
Output Voltage Programming
Output voltage for LDO is programmed by reference volt-
age and external voltage divider. The Fb3 pin is the in-
verting input of the error amplifier, which is internally ref-
erenced to 1.25V. The divider is ratioed to provide 1.25V
at the Fb3 pin when the output is at its desired value.
The output voltage is defined by using the following equa-
tion:
nection in the top layer with wide, copper filled areas.
The inductor, output capacitor and the MOSFET should
be close to each other as possible. This helps to reduce
the EMI radiated by the power traces due to the high
switching currents through them. Place input capacitor
directly to the drain of the high-side MOSFET, to reduce
the ESR replace the single input capacitor with two par-
allel units. The feedback part of the system should be
(
V OUT2 = V REF 3 1+
R 7
R 10
)
kept away from the inductor and other noise sources,
and be placed close to the IC. In multilayer PCB use
For:
V OUT2 = 2.5V
V REF = 1.25V
R 10 = 1K V
Results to R 7 =1K V
V OUT3
one layer as power ground plane and have a control cir-
cuit ground (analog ground), to which all signals are ref-
erenced. The goal is to localize the high current path to
a separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout at a
single point.
IRU3046
R 7
Fb3
R 10
Figure 9 - Programming the output voltage for LDO.
12
www.irf.com
Rev. 1.9
09/27/02
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