参数资料
型号: IRU3046CFTR
厂商: International Rectifier
文件页数: 8/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24TSSOP
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 450kHz
占空比: 90%
电源电压: 5 V ~ 12 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
包装: 剪切带 (CT)
产品目录页面: 1384 (CN2011-ZH PDF)
其它名称: *IRU3046CFTR
IRU3046CFCT
IRU3046
The R DS(ON) temperature dependency should be consid-
ered for the worst case operation. This is typically given
in the MOSFET data sheet. Ensure that the conduction
losses and switching losses do not exceed the package
ratings or violate the overall thermal budget.
Choose IRF7460 for control MOSFET and IRF7457 for
synchronous MOSFET. These devices provide low on-
From IRF7460 data sheet we obtain:
IRF7460
t r = 6.9ns
t f = 4.3ns
These values are taken under a certain condition test.
For more detail please refer to the IRF7460 and IRF7457
data sheets.
resistance in a compact SOIC 8-Pin package.
By using equation (7), we can calculate the switching
The MOSFETs have the following data:
losses.
IRF7460
V DSS = 20V
I D = 10A @ 75 8 C
R DS(ON) = 10m V @
V GS =10V
q = 1.8 for 150 8 C
IRF7457
V DSS = 20V
I D = 12A @ 70 8 C
R DS(ON) = 7.5m V @
V GS =10V
q = 1.5 for 150 8 C
P SW(MASTER) = 44.8mW
P SW(SLAVE) = 107.5mW
Feedback Compensation
The control scheme for master and slave channels is
based on voltage mode control, but the compensation of
(Junction Temperature) (Junction Temperature)
The total conduction losses for the master channel is:
P CON(MASTER) = 0.85W
The total conduction losses for the slave channel is:
P CON(SLAVE) = 0.77W
The control MOSFET contributes to the majority of the
switching losses in synchronous Buck converter. The
synchronous MOSFET turns on under zero-voltage con-
dition, therefore the turn on losses for synchronous
MOSFET can be neglected. With a linear approxima-
tion, the total switching loss can be expressed as:
these two feedback loops is slightly different.
The Master channel sets the output voltage and its feed-
back loop should take care of double pole introduced by
the output filter as a regular voltage mode control loop.
The goal is to provide a close loop transfer function with
the highest 0dB crossing frequency and adequate phase
margin. The slave feedback loop acts slightly different
and its goal is using the current information for current
sharing.
The master feedback loop sees the output filter. The out-
put LC filter introduces a double pole, -40dB/decade gain
slope above its corner resonant frequency, and a total
P SW =
V DS(OFF)
2
3
t r + t f 3 I LOAD
T
---(7)
phase lag of 180 8 (see Figure 5). The resonant frequency
of the LC filter expressed as follows:
Where:
V DS(OFF) = Drain to Source Voltage at off time
t r = Rise Time
F LC(MASTER) =
2 p
1
Lo 3 Co
---(8)
t f = Fall Time
T = Switching Period
I LOAD = Load Current
Figure 5 shows gain and phase of the LC filter. Since we
already have 180 8 phase shift just from the output filter,
the system risks being unstable.
V DS
90%
Gain
0dB
-40dB/decade
Phase
0 8
10%
V GS
F LC Frequency
-180 8
F LC
Frequency
t d (ON)
t r
t d (OFF)
t f
Figure 5 - Gain and phase of LC filter.
Figure 4 - Switching time waveforms.
8
www.irf.com
Rev. 1.9
09/27/02
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