参数资料
型号: IS61DDB42M18-250M3
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
中文描述: 2M X 18 DDR SRAM, 0.35 ns, PBGA165
封装: 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165
文件页数: 8/26页
文件大小: 460K
代理商: IS61DDB42M18-250M3
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
Timing Reference Diagram for Truth Table
Clock Truth Table
(Use the following table with the
Timing Reference Diagram for Truth Table
.)
Mode
Clock
Controls
Data Out / Data In
K
LD
t
t+1
t+2
Write B
A
K Clock
K Clock
LD
Cycle
NOP
Read A
B
R / W
Address
Data-In/Out (DQ)
C Clock
C Clock
BW
t
W
Q
A
Q
A+1
t
W+1
D
B
D
B+1
t
W+2
D
B+2
D
B+3
Q
A+2
Q
A+3
0,1,2,3
CQ Clock
CQ Clock
R/W
Q
A
/ D
B
Q
A+1
/ D
B+1
Q
A+2
/ D
B+2
Q
A+3
/ D
B+3
Stop Clock
Stop
X
X
Previous State
Previous State
Previous State
Previous State
No Operation (NOP)
L
H
H
H
High-Z
High-Z
High-Z
High-Z
Read B
L
H
L
H
Dout at C (t +
1.5)
Dout at C
(t + 2)
Dout at C
(t + 2.5)
Dout at C
(t + 3)
Write A
L
H
L
L
D
(t
W
+ 1)
D
(t
W
+ 1.5)
D
(t
W
+ 2)
D
(t
W
+ 2.5)
Notes
:
1. The internal burst counter is always fixed as two-bit.
2. X = don
t care; H = logic
1
; L = logic
0
.
3. A read operation is started when control signal R/W is active high.
4. A write operation is started when control signal R/W is active low.
5. Before entering into the stop clock, all pending read and write commands must be completed.
6. For timing definitions, refer to the
AC Characteristics
on page
16
. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K, K, C, and C.
相关PDF资料
PDF描述
IS61LF12832A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2I 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
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