参数资料
型号: IS61DDB42M18
厂商: Integrated Silicon Solution, Inc.
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
中文描述: 36字节(100万× 36
文件页数: 18/26页
文件大小: 460K
代理商: IS61DDB42M18
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
Read, Write, and NOP Timing Diagram
t
KLKH
t
KHKL
t
KHKH
t
CHQZ
t
CHQX
t
CHQX
t
CHQV
t
KHCH
t
KHDX
t
DVKH
t
KHAX
t
AVKH
t
KHIX
t
IVKH
t
KHKH
t
KLKH
t
KHKL
NOP
2
1
3
4
5
6
7
8
9
10
11
12
NOP
(burst of 4)
A0
A1
A2
A3
(Note 3)
(burst of 4)
(burst of 4)
Q01
Q03
Q11
Q13
Q14
Q12
Q04
Q02
D21
D24
D23
D22
Q31
Q33
Q32
K
K
t
KHKH
(burst of 4)
Read
NOP
Read
Write
Read
LD
R/W
SA
DQ
C
C
t
CHQV
t
CQHQZ
t
CQHQX
t
CQHQV
t
CHCQH
t
KHKH
CQ
CQ
Don
t Care
Undefined
Notes:
1. Q01 refers to the output from address A. Q02 refers to the output from the next internal burst address following A.
2. Outputs are disabled (high impedance) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it
might be required to prevent bus contention.
相关PDF资料
PDF描述
IS61DDB42M18-250M3 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61LF12832A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2I 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B3 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
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