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参数资料
| 型号： | IS61DDB42M18 |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs |
| 中文描述： | 36字节（100万× 36 |
| 文件页数： | 5/26页 |
| 文件大小： | 460K |
| 代理商： | IS61DDB42M18 |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
5
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
The write data is provided in a
‘
late write
’
mode; that is, the data-in corresponding to the first address of the
burst, is presented 1 cycle later or at the rising edge of the following K clock. The data-in corresponding to the
second write burst address follows next, registered by the rising edge of K. The third data-out is clocked by
the subsequent rising edge of the K clock, and the fourth data-out is clocked by the subsequent rising edge of
the K clock.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the third write cycle. A read cycle to the last two write address produces data from the write
buffers. The SRAM maintains data coherency.
During a write, the byte writes independently control which byte of any of the four burst addresses is written
(see
X18/X36 Write Truth Tables
on page
9
and
Timing Reference Diagram for Truth Table
on page
8
).
Whenever a write is disabled (R/W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250
results in a driver impedance of 50
. The allowable range
of RQ to guarantee impedance matching is between 175
and 350
, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics
on page 15. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to V
DDQ
to obtain a minimum impedance setting. ZQ must never
be connected to V
SS
.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Clock Consideration
This device uses an internal DLL for maximum output data valid window. It can be placed in a stopped-clock
mode to minimize power and requires only 1024 cycles to restart.
No clocks can be issued until V
DD
reaches its allowable operating range.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K control the output timings.
Either clock pair must have both polarities switching and must never connect to V
REF
, as they are not differ-
ential clocks.
相关PDF资料 |
PDF描述 |
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| IS61DDB42M18-250M3 | 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs |
| IS61LF12832A | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF12832A-6.5B2 | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF12832A-6.5B2I | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
| IS61LF12832A-6.5B3 | 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61DDB42M18-250M3 | 功能描述:静态随机存取存储器 36Mb 2Mbx18 DDR II Sync 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61DDB42M18-250M3L | 功能描述:静态随机存取存储器 36M (2Mx18) 250ns DDR II Sync 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61DDB42M18A-250M3L | 功能描述:静态随机存取存储器 36Mb 2Mx18 165ball DDR II Sync 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| IS61DDB42M36 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs |
| IS61DDB42M36-250M3 | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs |
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