参数资料
型号: ISD4003-08MEI
厂商: WINBOND ELECTRONICS CORP
元件分类: 音频合成
英文描述: 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
封装: 8 X 13.40 MM, PLASTIC, TSOP1-28
文件页数: 18/37页
文件大小: 392K
代理商: ISD4003-08MEI
25
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
8.6.2
EEARH and EEARL – EEPROM Address Register Atmel
ATmega325A/325PA/3250A/3250PA/625A/645P/6450A/6450P
Bits 15:11 – Reserved
These bits are reserved bits in the
ATmega325A/325PA/3250A/3250PA/645A/645P/6450A/6450P and will always read as zero.
Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1/2K bytes EEPROM
space. The EEPROM data bytes are addressed linearly between 0 and 1023/2047. The initial value of EEAR is
undefined. A proper value must be written before the EEPROM may be accessed.
Note:
1. EEAR10 is only valid for ATmega645A/ATmega645P/ATmega6450A/ATmega6450P.
8.6.3
EEDR – EEPROM Data Register
Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the
address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from
the EEPROM at the address given by EEAR.
8.6.4
EECR – EEPROM Control Register
Bits 7:4 – Reserved
These bits are reserved and will always read as zero.
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero dis-
ables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is
set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is
Bit
1514131211
10
9
8
0x22 (0x42)
EEAR9
EEAR8
EEARH
0x21 (0x41)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
76
543
2
1
0
Read/Write
RRRR
R
R/W
Initial Value
0
X
XXXXX
X
Bit
765
432
10
0x20 (0x40)
MSB
LSB
EEDR
Read/Write
R/W
Initial Value
000
00
Bit
765
43
2
1
0
0x1F (0x3F)
EERIE
EEMWE
EEWE
EERE
EECR
Read/Write
RRRR
R/W
Initial Value
0
X
0
相关PDF资料
PDF描述
ISD4003-08MSI 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28
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