- 您现在的位置：买卖IC网 > PDF目录176103 > ISD4003-08MEI (WINBOND ELECTRONICS CORP) 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28 PDF资料下载
参数资料
| 型号： | ISD4003-08MEI |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 音频合成 |
| 英文描述： | 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28 |
| 封装： | 8 X 13.40 MM, PLASTIC, TSOP1-28 |
| 文件页数： | 29/37页 |
| 文件大小： | 392K |
| 代理商： | ISD4003-08MEI |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页
35
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
9.11
Register description
9.11.1
OSCCAL – Oscillator Calibration Register
Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia-
tions from the oscillator frequency. A pre-programmed calibration value is automatically written to this register
during chip reset, giving the Factory calibrated frequency as specified in Table 28-11 on page 296. The application
software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies
as specified in Table 28-11 on page 296. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8MHz. Otherwise, the EEPROM
or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre-
quency in that range, and a setting of 0x7F gives the highest frequency in the range.
9.11.2
CLKPR – Clock Prescale Register
Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated
when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after
it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither
extend the time-out period, nor clear the CLKPCE bit.
Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the
master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 9-14.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the
CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will
be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start
up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency
of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless
Bit
765
432
10
(0x66)
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
Initial Value
Device Specific Calibration Value
Bit
7
6
5
4
3210
(0x61)
CLKPCE
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
CLKPR
Read/Write
R/W
RRR
R/W
Initial Value
0
See Bit Description
相关PDF资料 |
PDF描述 |
|---|---|
| ISD4003-08MSI | 480 SEC, SPEECH SYNTHESIZER WITH RCDG, PDSO28 |
| ISD4003-04MZD | 240 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19 |
| ISD4003-04MZI | 240 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19 |
| ISD4003-05MZD | 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19 |
| ISD4003-05MZI | 300 SEC, SPEECH SYNTHESIZER WITH RCDG, PBGA19 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISD4003-08MEIR | 功能描述:IC VOICE REC/PLAY 8MIN IN 28TSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 语音录制和重放 系列:ISD4003 标准包装:14 系列:- 接口:串行 滤波器通频带:1.7kHz 持续时间:8 ~ 32 秒 安装类型:通孔 封装/外壳:28-DIP（0.300"，7.62mm） 供应商设备封装:28-PDIP 其它名称:90-21300+000 |
| ISD4003-08MEY | 功能描述:IC VOICE REC/PLAY 8MIN 28-TSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 语音录制和重放 系列:ISD4003 标准包装:14 系列:- 接口:串行 滤波器通频带:1.7kHz 持续时间:8 ~ 32 秒 安装类型:通孔 封装/外壳:28-DIP（0.300"，7.62mm） 供应商设备封装:28-PDIP 其它名称:90-21300+000 |
| ISD4003-08MEYI | 功能描述:IC VOICE REC/PLAY 8MIN 28-TSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 语音录制和重放 系列:ISD4003 标准包装:14 系列:- 接口:串行 滤波器通频带:1.7kHz 持续时间:8 ~ 32 秒 安装类型:通孔 封装/外壳:28-DIP（0.300"，7.62mm） 供应商设备封装:28-PDIP 其它名称:90-21300+000 |
| ISD4003-08MP | 功能描述:IC VOICE REC/PLAY 8MIN 28-DIP RoHS:否 类别:集成电路 (IC) >> 接口 - 语音录制和重放 系列:ISD4003 标准包装:14 系列:- 接口:串行 滤波器通频带:1.7kHz 持续时间:8 ~ 32 秒 安装类型:通孔 封装/外壳:28-DIP（0.300"，7.62mm） 供应商设备封装:28-PDIP 其它名称:90-21300+000 |
| ISD400308MPD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Chip Voice Record/Playback Devices 2- to 16-Minute Durations |
发布紧急采购，3分钟左右您将得到回复。