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参数资料
| 型号： | ISL1219 |
| 厂商： | Intersil Corporation |
| 英文描述： | Low Power RTC with Battery Backed SRAM and Event Detection(具有电池供电的SRAM和事件检测功能的低功率RTC) |
| 中文描述： | 低功耗RTC与电池供电的SRAM和事件检测（具有电池供电的SRAM的和事件检测功能的低功率实时时钟） |
| 文件页数： | 4/25页 |
| 文件大小： | 373K |
| 代理商： | ISL1219 |
4
FN6314.1
August 14, 2006
Power-Down Timing
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
(Note 5)
MAX
UNITS
NOTES
V
DD SR-
V
DD
Negative Slew Rate
10
V/ms
4
I
2
C Interface Specifications
Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 4)
MAX
UNITS
NOTES
V
IL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x
V
DD
V
V
IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x
V
DD
V
DD
+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05 x
V
DD
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
DD
= 5V, I
OL
= 3mA
0.4
V
Cpin
SDA and SCL Pin Capacitance
T
A
= 25°C, f = 1MHz, V
DD
= 5V,
V
IN
= 0V, V
OUT
= 0V
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
DD
,
until SDA exits the 30% to 70% of V
DD
window.
900
ns
t
BUF
Time the Bus Must be Free before the
Start of a New Transmission
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing 70%
of V
DD
during the following START
condition.
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
DD
crossing.
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
DD
crossing.
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of V
DD
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of V
DD
to SCL falling edge crossing
70% of V
DD
.
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of
V
DD
window, to SCL rising edge
crossing 30% of V
DD.
100
ns
t
HD:DAT
Input Data Hold Time
From SCL falling edge crossing 30%
of V
DD
to SDA entering the 30% to
70% of V
DD
window.
0
900
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
V
DD
, to SDA rising edge crossing 30%
of V
DD
.
600
ns
t
HD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
DD
.
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30%
of V
DD
, until SDA enters the 30% to
70% of V
DD
window.
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
DD.
20 +
0.1 x Cb
300
ns
7
ISL1219
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