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参数资料
| 型号： | ISL5239 |
| 厂商： | Intersil Corporation |
| 英文描述： | Pre-Distortion Linearizer |
| 中文描述： | 预失真线性化电路 |
| 文件页数： | 5/31页 |
| 文件大小： | 653K |
| 代理商： | ISL5239 |
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5
A<5:0>
I
6-bit address bus that operates with P<15:0>, CS, RD, and WR to write to and read from the devices internal
control registers. Bit 5 is the MSB.
CS
I
Chip Select. (active low). Enables device to respond to
μ
P access by enabling read or write operations.
WR
I
Write Strobe, (active low). The data on P<15:0> is written to the destination selected by A<5:0> on the rising
edge of WR when CS is asserted (low).
RD
I
Read Strobe (Active Low). The data at the address selected by A(5:0) is placed on P<15:0> when RD is
asserted (low) and CS is asserted (low).
BUSY
O
μ
P Busy. (Active Low) Indicates that the
μ
P interface is busy. The device asserts BUSY during a read operation
to indicate that the output data on P<15:0> is not ready, and it asserts this signal during a write operation to
indicate that it is not available for another read or write operation yet.
EXTERNAL SERIAL INTERFACE
SERCLK
O
Serial Clock. Clock signal provided to external device for serial input and output, derived from rising edge of
CLK.
SERSYNC
O
Serial Sync. Active high single-cycle pulse that is time coincident with the first sample of the 32-bit serial data
frame. Derived from by rising edge of CLK.
SEROUT
O
Serial Output. Output data bit for the serial interface. Derived from the rising edge of CLK.
SERIN
I
Serial Input.Input data bit for serial interface. Derived from rising edge of CLK.
FEEDBACK INTERFACE
FB<19:0>
I
Feedback Input Data. Parallel or serial data to be stored in the feedback memory. In parallel mode, all 20-
bits are stored on the rising edge of FBCLK. In serial mode, bit 0 is serial input data and bit 1 is serial sync,
sampled at the rising edge of FBCLK.
FBCLK
I
Input clock used for sampling the FB<19:0> pins.
TRIGGER INTERFACE
TRIGIN
I
Trigger input. Hardwired trigger source to be used to trigger an input/feedback capture. Sampled internally
with rising edge of CLK.
TRIGOUT
O
Trigger output. Indicated that the capture system has been triggered, either internally or externally.
DATA INPUT
IIN<17:0>
I
I input data. Real component of the complex input sample when input format is parallel. Alternating real and
imaginary when input format is muxed. Selectable as 2’s complement or offset binary.
QIN<17:0>
I
Q input data. Imaginary component of the complex input sample when input format is parallel. Unused in serial
input format.
ISTRB
I
I data strobe. (active high). Used in the muxed input format. When asserted, the input data buses contains valid
I data.
CLKOUT
O
Input data clock. Output clock for the data source driving the IIN<17:0> and QIN<17:0> inputs. Input data
busses sampled on the rising edge of CLK that generates the rising edge of CLKOUT.
DATA OUTPUT
IOUT<17:0>
I
I output data. Real component of the complex output sample driven by the rising edge of CLK. Selectable as
2’s complement or offset binary.
QOUT<17:0>
I
Q output data. IMaginary component of the complex output sample driven by the rising edge of CLK. Selectable
as 2’s complement or offset binary.
TEST ACCESS
DCTEST
O
DC tree output. NAND tree output for DC threshold test. Do not connect for normal operation.
JTAG TEST ACCESS PORT
TMS
I
JTAG Test Mode Select. Internally pulled up.
TDI
I
JTAG Test Data In. Internally pulled up.
TCK
I
JTAG Test Clock.
TRST
I
JTAG Test Reset (Active Low). Internally pulled-up.
TDO
O
JTAG Test Data Out.
Pin Descriptions
(Continued)
NAME
TYPE
DESCRIPTION
ISL5239
相关PDF资料 |
PDF描述 |
|---|---|
| ISL5239KI | Pre-Distortion Linearizer |
| ISL5239KIZ | Pre-Distortion Linearizer |
| ISL5416 | Four-Channel Wideband Programmable DownConverter |
| ISL5416EVAL | Four-Channel Wideband Programmable DownConverter |
| ISL5416KI | Four-Channel Wideband Programmable DownConverter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL5239EVAL1 | 功能描述:EVALUATION BOARD FOR ISL5239 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| ISL5239KI | 功能描述:音频 DSP PA LINEARIZER IND TEMP 1 0MM PITCH RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| ISL5239KIZ | 功能描述:音频 DSP PA LINEARIZER IND 0MM PITCH BGA PACKAG RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| ISL5314 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Digital Synthesizer |
| ISL5314_05 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Digital Synthesizer |
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