参数资料
型号: ISL55143IRZ-T
厂商: Intersil
文件页数: 3/14页
文件大小: 0K
描述: IC COMP CMOS HS 18V 36-TQFN
标准包装: 4,000
类型: 窗口
元件数: 4
电压 - 电源,单路/双路(±): 10 V ~ 18 V
电压 - 输入偏移(最小值): 50mV @ -3V,12V
电流 - 输入偏压(最小值): 0.025µA @ -3V,12V
电流 - 静态(最大值): 12.5mA
传输延迟(最大): 15ns
工作温度: -40°C ~ 85°C
封装/外壳: 36-WFQFN 裸露焊盘
安装类型: 表面贴装
包装: 带卷 (TR)
11
FN6230.3
April 4, 2013
ISL55141, ISL55142, ISL55143
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
B
A
17
8
14
C
PLANE
SEATING
0.10 C
0.10
CB A
H
PIN #1
I.D. MARK
5.00 ±0.10
4.40 ±0.10
0.25 +0.05/-0.06
6.40
0.20 C B A
0.05
0°-8°
GAUGE
PLANE
SEE
0.90 +0.15/-0.10
0.60 ±0.15
0.09-0.20
5
2
3
1
3
1.00 REF
0.65
1.20 MAX
0.25
0.05 MIN
0.15 MAX
(1.45)
(5.65)
(0.65 TYP)
(0.35 TYP)
DETAIL "X"
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
NOTES:
END VIEW
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