参数资料
| 型号： | ISL6217CVZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM INTEL PENT 38-TSSOP |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium? IMVP-IV，IMVP+ |
| 输入电压： | 5.5 V ~ 25 V |
| 输出数： | 1 |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
ISL6217
VID[0..5]
V CC_CORE
Current VID Code
< 600ns
Current Voltage Level
New VID Code
New Voltage Level
PGOOD
FIGURE 5.
VID[0..5]
STP_CPU#
(DSEN#)
HIGH
PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID Code remains the same
V CC_CORE
VID Command Voltage
VDeep Sleep
<30us
FIGURE 6.
VID[0..5]
STP_CPU#
(DSEN#)
CORE VOLTAGE SLEWING TO 98.8% OF PROGRAMMED VID VOLTAGE FOR A LOGIC LEVEL LOW ON DSEN
VID Code remains the same
Deeper Sleep Mode
DPRSLPVR
(DRSEN)
Short DPRSLP causes
V CC_CORE
V Deep Sleep
V Deeper Sleep
VCC-CORE
to ramp up
FIGURE 7.
VCORE RESPONSE FOR DEEPER SLEEP COMMAND
A logic low signal present on STPCPU# (pin DSEN#), with
a logic low signal on DPRSLPVR (pin DRSEN), signals the
ISL6217 to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin.
A logic high on DPRSLPVR, (pin DRSEN) with a logic low
signal on STPCPU# (pin DSEN#), signals the ISL6217
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in the “STV, DSV and
DRSV” section of this document.
Deep Sleep Enable-DSEN# and Deeper Sleep
Enable - DRSEN
Table 2 shows logic states controlling modes of operation.
Figure 6 and Figure 7 shows the timing for transitions
11
entering and exiting Deep Sleep Mode and Deeper Sleep
Mode. This is controlled by the system signals STPCPU#
and DPRSLPVR. ISL6217 pins DSEN#, (Deep Sleep
Enable #) and DRSEN, (Deeper Sleep Enable), are
connected to these 2 signals, respectively.
When DSEN# is logic high, and DRSEN is logic low, the
controller will operate in Active Mode and regulate the
output voltage to the VID commanded DAC voltage, minus
the voltage “Droop” as determined by the load current.
Voltage “Droop” is the reduction of output voltage
proportional to output current.
When a logic low is detected at the DSEN# and DRSEN
pins, the controller will regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”. If the PWRCH
pin is connected to the DSEN# pin then the controller will
also switch to single channel operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6217EVAL2 | 制造商:Intersil Corporation 功能描述:PURCHASE ISL6216EVAL1, ISL6217EVAL2 OR ISL6218EVAL2 WITH IS - Bulk |
| ISL6218 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Precision Single-Phase Buck PWM Controller for Intel Mobile Voltage Positioning IMVP-IV and IMVP-IV |
| ISL6218CRZ | 功能描述:电流型 PWM 控制器 P6 MULTIPHS BUCK PWM CNTRLR FOR IMVP4 RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6218CRZ-T | 功能描述:电流型 PWM 控制器 P6 MULTIPHS BUCK PWM CNTRLR FOR IMVP4 RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6218CV | 功能描述:IC CTRLR INTEL PENT M 38-TSSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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