参数资料
| 型号： | ISL6237IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/35页 |
| 文件大小： | 0K |
| 描述： | IC MAIN PWR CTRLR QUAD 32-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 5.5 V ~ 25 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
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ISL6237
Pin Descriptions
PIN
1
2
3
4
5
6
7
NAME
REF
TON
VCC
EN_LDO
NC
VIN
LDO
FUNCTION
2V Reference Output. Bypass to GND with a 0.1μF (min) capacitor. REF can source up to 50μA for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.
Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively.)
Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1μF ceramic capacitor.
LDO Enable Input. The LDO is enabled if EN_LDO is within logic high level and disabled if EN_LDO is less than the
logic low level.
No connect.
Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power
the linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied
to OUT1. Connect VIN to the battery input and bypass with a 1μF capacitor.
Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7 Ω switch. The LDO regulate at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5 Ω switch. Bypass LDO output with a minimum of
4.7μF ceramic.
8
LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1
BOOT1
LGATE1
PVCC
NC
GND
PGND
BYP is the switchover source voltage for the LDO when LDOREFIN connected to GND or VCC. Connect BYP to 5V if
LDOREFIN is tied GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.
SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.
SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over
a 0.2V to 2V range. There is an internal 5μA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed
200mV threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.
SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start).
Drive EN1 below 0.8V to clear fault level and reset the fault latches.
High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.
Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the “Typical Application
Circuits” starting on page 21 (Figures 62, 63 and 64). See “MOSFET Gate Drivers (UGATE_, LGATE_)” on page 28.
SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.
PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin and
bypass to PGND with a 1μF MLCC ceramic capacitor. Refer to Figure 65 - A switch connects PVCC to VCC with 10 Ω
when in normal operation and is disconnected when in shutdown mode. An external 10 Ω resistor from PVCC to VCC
is prohibited as it will create a leakage path from VIN to GND in shutdown mode.
No connect.
Analog Ground for both SMPS_ and LDO. Connect externally to the underside of the exposed pad.
Power Ground for SMPS_ controller. Connect PGND externally to the underside of the exposed pad.
7
FN6418.4
March 18, 2008
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