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| 型号： | ISL62392HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28TQFN |
| 标准包装： | 6,000 |
| 应用： | 电源控制器 |
| 电源电压： | 5.5 V ~ 25 V |
| 电流 - 电源： | 150µA |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL62391, ISL62392, ISL62391C, ISL62392C
Theory of Operation
Three Output Controller
The ISL62391, ISL62392, ISL62391C and ISL62392C
generate three regulated output voltages. Two are produced
with switch-mode power supplies (SMPS), and the third by a
low dropout linear regulator (LDO). An additional 5V LDO
(PVCC) is used to power the chip during operation, allowing
the ISL62391, ISL62392, ISL62391C and ISL62392C to
regulate all outputs from a single power source (VIN) with no
need for a separate quiescent supply. This makes the
ISL62391, ISL62392, ISL62391C and ISL62392C an ideal
choice as system regulator for notebook PCs. Because the
two SMPS channels are identical and almost entirely
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor, R W , connected across the FSET and
GND pins. The V R, V COMP, and V W signals feed into a
window comparator in which V COMP is the lower threshold
voltage and V W is the higher threshold voltage. Figure 23
shows PWM pulses being generated as V R traverses the
V W and V COMP thresholds. The PWM switching frequency
is proportional to the slew rates of the positive and negative
slopes of V R; it is inversely proportional to the voltage
between V W and V COMP. Equation 3 illustrates how to
calculate the window size based on output voltage and
frequency set resistor.
F SW = ------------------
R W = ---------------------
independent, all conclusions drawn apply to both channels
unless otherwise noted.
Modulator and Switching Frequency
The ISL62391, ISL62392, ISL62391C and ISL62392C
modulator feature Intersil’s R 3 technology, a hybrid of fixed
frequency PWM and variable frequency hysteretic control.
Intersil’s R 3 technology can simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients. The R 3 modulator
synthesizes an AC signal, V R , which is an analog
representation of the output inductor ripple current. The
duty-cycle of V R is the result of charge and discharge
current through a ripple capacitor, C R . The current through
C R is provided by a transconductance amplifier that
measures the VIN and VO pin voltages. The positive slope
of V R can be written as Equation 1:
V W = g m ? V OUT ? ( 1 – D ) ? R W
The frequency can be expressed in Equation 4:
1
K ? R W
Inverting Equation 4 allows easy selection of R W for a
desired F SW :
1
K ? F SW
For Equations 3 through 5:
g m = 1.66μs
K = 1.7 x 10 -10 (±20%)
D = V OUT /V IN
Power-On Reset
(EQ. 3)
(EQ. 4)
(EQ. 5)
V RPOS = g m ? ( V IN – V OUT )
(EQ. 1)
The ISL62391, ISL62392, ISL62391C and ISL62392C are
disabled until the voltage at the VIN pin has increased above
The negative slope of V R can be written as Equation 2:
the rising power-on reset (POR) threshold. Conversely, the
V RNEG = g m ? V OUT
(EQ. 2)
controller will be disabled when the voltage at the VIN pin
decreases below the falling POR threshold.
Where g m is the gain of the transconductance amplifier.
In addition to VIN POR, the PVCC pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
RIPPLE CAPACITOR VOLTAGE C R
WINDOW VOLTAGE V W
(WRT V COMP )
ERROR AMPLIFIER
VOLTAGE V COMP
PWM
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62391, ISL62392, ISL62391C and ISL62392C use a
digital soft-start circuit to ramp the output voltage of each
SMPS to the programmed regulation setpoint at a
predictable slew rate. The slew rate of the soft-start
sequence has been selected to limit the in-rush current
through the output capacitors as they charge to the desired
regulation voltage. When the EN pins are pulled above their
rising thresholds, the PGOOD Soft-Start Delay, t SS , starts and
the output voltage begins to rise. The FB pin ramps to 0.6V in
approximately 1.5ms and the PGOOD pin goes to high
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
13
impedance approximately 1.25ms after the FB pin voltage
reaches 0.6V.
FN6666.7
August 22, 2013
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