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参数资料
| 型号： | ISL62392HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/21页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28TQFN |
| 标准包装： | 6,000 |
| 应用： | 电源控制器 |
| 电源电压： | 5.5 V ~ 25 V |
| 电流 - 电源： | 150µA |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL62391, ISL62392, ISL62391C, ISL62392C
Functional Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Bottom
Pad
NAME
PGOOD
FSET2
FCCM
VCC
LDO3EN
FSET1
FB1
VOUT1
ISEN1
OCSET1
EN1
PHASE1
UGATE1
BOOT1
LGATE1
LDO3
VIN
PVCC
PGND
LGATE2
BOOT2
UGATE2
PHASE2
EN2
OCSET2
ISEN2
VOUT2
FB2
GND
FUNCTION
Open-drain power-good status outputs. Connect to VCC through a 100k resistor. Output will be high when all outputs are
within regulation with no faults detected.
Frequency control input for SMPS2. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
Logic input to control efficiency mode. Logic high forces continuous conduction mode (CCM). Logic low allows full
discontinuous conduction mode (DCM). Float this pin for ultrasonic DCM operation.
Analog power supply input for reference voltages and currents. Bypass to ground with a 1μF ceramic capacitor near the IC.
Logic input for enabling and disabling the LDO3 linear regulator. Positive logic input.
Frequency control input for SMPS1. Connect a resistor to ground to program the switching frequency. The pin output is
a pulsed current and requires a decoupling capacitor to average the signal.
SMPS1 feedback input used for output voltage programming and regulation.
SMPS1 output voltage sense input. Used for soft-discharge.
SMPS1 DCR current sense input. Used for overcurrent protection and R 3 regulation.
Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS1.
Logic input to enable and disable SMPS1. A logic high will immediately enable SMPS1. Floating this pin will enable
SMPS1 only after SMPS2 has been enabled and achieved regulation. A logic low disables SMPS1.
SMPS1 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS1.
High-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 switching FET.
SMPS1 bootstrap input for the switching NMOS gate drivers. Connect to SMPS1 PHASE with a ceramic capacitor of 0.22μF.
Low-side NMOS gate drive output for SMPS1. Connect to the gate of the SMPS1 synchronous FET.
3.3V linear regulator output, capable of providing 100mA continuous current. Bypass to ground with a 4.7μF ceramic capacitor.
Feed-forward input for line voltage transient compensation. Connect to the power train input voltage.
5V power source for SMPS gate drive current. Bypass to ground with a 4.7μF ceramic capacitor.
Power ground for SMPS1 and SMPS2. This provides a return path for synchronous FET switching currents.
Low-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 synchronous FET.
SMPS2 bootstrap input for the switching NMOS gate drivers. Connect to SMPS2 PHASE with a ceramic capacitor of 0.22μF.
High-side NMOS gate drive output for SMPS2. Connect to the gate of the SMPS2 switching FET.
SMPS2 switching node for high-side gate drive return and synthetic ripple modulation. Connect to the switching NMOS
source, the synchronous NMOS drain, and the output inductor for SMPS2.
Logic input to enable and disable SMPS2. A logic high will immediately enable SMPS2. Floating this pin will enable
SMPS2 only after SMPS1 has been enabled and achieved regulation. A logic low disables SMPS2.
Input from DCR current-sensing network used to program the overcurrent shutdown threshold for SMPS2.
SMPS2 DCR current sense input. Used for overcurrent protection and R 3 regulation.
SMPS2 output voltage sense input. Used for soft-discharge and switchover for PVCC 5V LDO.
SMPS2 feedback input used for output voltage programming and regulation.
Analog ground for analog and logic signals.
6
FN6666.7
August 22, 2013
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相关代理商/技术参数 |
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