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参数资料
| 型号： | ISL62392HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 20/21页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CONTROLLER 28TQFN |
| 标准包装： | 6,000 |
| 应用： | 电源控制器 |
| 电源电压： | 5.5 V ~ 25 V |
| 电流 - 电源： | 150µA |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL62391, ISL62392, ISL62391C, ISL62392C
R OCSET to the phase-node side pad of the inductor, and
connect C SEN to the output side pad of the inductor. The
ISEN resistor should also be connected to the output pad of
the inductor with a separate trace. Connect the OCSET pin
to the common node of node of R OCSET and C SEN .
For resistive current sensing, connect R OCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the V OUT side of the resistor
pad.
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 7 and 28), and VOUT (Pins 8 and 27)
BOOT (Pins 14 and 21), UGATE (Pins 13 and 22), and
PHASE (Pins 12 and 23)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
The VOUT pin is used to generate the R 3 synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
compensation components close to the VOUT, FB, and GND
pins, keeping the high impedance trace short.
FSET (Pins 2 and 6)
This pin requires a quiet environment. The resistor R FSET
and capacitor C FSET should be placed directly adjacent to
this pin. Keep fast moving nodes away from this pin.
LGATE (Pins 15 and 20)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN6666.7
August 22, 2013
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