参数资料
型号: ISL6261EVAL1Z
厂商: Intersil
文件页数: 4/34页
文件大小: 0K
描述: EVAL BOARD FOR ISL6261 1 QFN
标准包装: 1
系列: *
ISL6261
Electrical Specifications
V DD = 5V, T A = -10°C to +100°C, Unless Otherwise Specified. (Continued)
PARAMETER
Error Amp Gain-Bandwidth Product
SYMBOL
GBW
C L = 20pF
TEST CONDITIONS
MIN
-
TYP
18
MAX
-
UNITS
MHz
(Note 3)
Error Amp Slew Rate (Note 3)
FB Input Current
SR
I IN(FB)
C L = 20pF
-
-
5.0
10
-
150
V/μs
nA
SOFT-START CURRENT
Soft-start Current
I SS
-46
-41
-36
μA
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
I GV
I C4
I C4EA
I C4EB
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
±175
-46
36
175
±200
-41
41
200
±225
-36
46
225
μA
μA
μA
μA
GATE DRIVER DRIVING CAPABILITY (Note 4)
UGATE Source Resistance
UGATE Source Current
UGATE Sink Resistance
UGATE Sink Current
LGATE Source Resistance
LGATE Source Current
LGATE Sink Resistance
LGATE Sink Current
UGATE to PHASE Resistance
R SRC(UGATE)
I SRC(UGATE)
R SNK(UGATE)
I SNK(UGATE)
R SRC(LGATE)
I SRC(LGATE)
R SNK(LGATE)
I SNK(LGATE)
R P(UGATE)
500mA Source Current
V UGATE_PHASE = 2.5V
500mA Sink Current
V UGATE_PHASE = 2.5V
500mA Source Current
V LGATE = 2.5V
500mA Sink Current
V LGATE = 2.5V
-
-
-
-
-
-
-
-
-
1
2
1
2
1
2
0.5
4
1.1
1.5
-
1.5
-
1.5
-
0.9
-
-
Ω
A
Ω
A
Ω
A
Ω
A
k Ω
GATE DRIVER SWITCHING TIMING (Refer to Timing Diagram)
UGATE Turn-on Propagation Delay
LGATE Turn-on Propagation Delay
t PDHU
t PDHL
PV CC = 5V, Output Unloaded
PV CC = 5V, Output Unloaded
20
7
30
15
44
30
ns
ns
BOOTSTRAP DIODE
Forward Voltage
Leakage
V DDP = 5V, Forward Bias Current = 2mA
V R = 16V
0.43
-
0.58
-
0.67
1
V
μ A
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
Undervoltage Threshold
V OL
I OH
tpgd
O VH
O VHS
UV f
I PGOOD = 4mA
P GOOD = 3.3V
CLK_EN# Low to PGOOD High
V O rising above setpoint >1ms
V O rising above setpoint >0.5μs
I(Rbias) = 10μA
DROOP rising above OCSET >120μs
V O below set point for >1ms
-
-1
5.5
160
1.675
9.8
-3.5
-360
0.11
-
6.8
200
1.7
10
-300
0.4
1
8.1
240
1.725
10.2
3.5
-240
V
μA
ms
mV
V
μA
mV
mV
(VDIFF-SOFT)
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
V IL(3.3V)
-
-
1
V
Input Low
VR_ON, DPRSLPVR and PGD_IN
V IH(3.3V)
2.3
-
-
V
Input High
4
FN9251.1
September 27, 2006
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