参数资料
型号: ISL6266HRZ
厂商: Intersil
文件页数: 23/30页
文件大小: 0K
描述: IC CORE CTRLR 2PHASE 48-QFN
标准包装: 43
应用: 转换器,Intel IMVP-6
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.3 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6266, ISL6266A
ISEN1
ISEN1
ISEN2
ISEN2
OC
-
+
10μA
OCSET
R OCSET
VO'
I PHASE1
L1
+
Vdcr 1
-
R PAR
C L1
INTERNAL TO
ISL6266
+
+
+
1 -
+
1 -
VSUM
+
DROOP DFB
-
DROOP
R drp2
VSUM
R SERIES
Cn
RS
VSUM
I PHASE2
RS
VSUM
R L1
ISEN1
L 2
R L2
DCR
RO1
VO'
DCR
+ -
Vdcr 2
R O2
V OUT
VDIFF
RTN
VSEN
VO'
R drp1
R NTC
VO'
ISEN2
C L2
VO'
C BULK
82nF
0.018μF
R OPN2
0.018μF
10
R opn1
V CC_SENSE
V SS_SENSE
TO V OUT
TO PROCESSOR
SOCKET KELVIN
CONNECTIONS
ESR
FIGURE 37. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6266A are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are V CC_SENSE and
V SS_SENSE respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be treated as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising/falling
voltage nodes (switching nodes) and other noisy traces. To
Intersil recommends the use of the R OPN1 and R OPN2
connected to V OUT and ground as shown in Figure 37.
These resistors provide voltage feedback in the event that
the system is powered up without a processor installed.
These resistors typically range from 20 Ω to 100 Ω .
Setting the Switching Frequency - FSET
The R 3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due to changes in input and output
voltage and output current, but this variation is normally less
than 10% in continuous conduction mode.
See Figure 32. The resistor connected between the VW and
COMP pins of the ISL6266A adjusts the switching window,
and therefore adjusts the switching frequency. The R FSET
resistor that sets up the switching frequency of the converter
operating in CCM can be determined using Equation 7,
where R FSET is in k Ω and the switching frequency is in kHz.
R FSET ( k Ω ) = ? ----------------------------- ?
achieve optimum performance, place common mode and
differential mode RC filters to analog ground on VSEN and
RTN as shown in Figure 37. The filter resistors should be
? 2232 ?
F SW ( kHz ) – 1.1202
(EQ. 7)
10 Ω so that they do not interact with the 50k Ω input
resistance of the differential amplifier. The filter resistor may
be inserted between V CC_SENSE and the VSEN pin.
Another option is to place to the filter resistor between
Vcc_sense and VSEN pin and between V SS_SENSE and
RTN pin. The need for RC filters really depends on the
actual board layout and noise environment.
23
Equation 7 is only a rough estimate of actual frequency. It
should be used to choose an R FSET value in the vicinity of
the desired switching frequency. Empirical fine tuning may
be necessary to achieve the actual frequency target. In
addition, droop amplifier gain may slightly affect the
switching frequency. Equation 7 is derived using the droop
gain seen on the ISL6266AEVAL1Z REV A evaluation
board.
FN6398.3
June 14, 2010
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