参数资料
型号: ISL6268EVAL1Z
厂商: Intersil
文件页数: 7/14页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL6268
标准包装: 1
系列: Robust Ripple Regulator™ (R³)
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 1.2V
电流 - 输出: 5A
输入电压: 7 ~ 25 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6268
ISL6268
Theory of Operation
Modulator
The ISL6268 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R 3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust Ripple
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R 3
modulator synthesizes an AC signal V R , which is an ideal
representation of the output inductor ripple current. The
duty-cycle of V R is the result of charge and discharge
current through a ripple capacitor C R . The current through
C R is provided by a transconductance amplifier g m that
measures the VIN and VO pin voltages. The positive slope
of V R can be written as:
Power-On Reset
The ISL6268 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) V CCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR V CCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6268 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage V ENTHR the PGOOD
Soft-Start Delay T SS begins and the output voltage begins to
rise. The output voltage enters regulation in approximately
V RPOS = ( g m ) ? ( V IN – V OUT )
The negative slope of V R can be written as:
(EQ. 1)
1.5ms and the PGOOD pin goes to high impedance once T SS
has elapsed.
V RNEG = g m ? V OUT
(EQ. 2)
where g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V W is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as V R traverses the V W and
V COMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V R; the PWM switching frequency is inversely
proportional to the voltage between V W and V COMP.
1.5ms
VOUT
VCC and PVCC
EN
PGOOD
2.75ms
FIGURE 3. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
supplying regulated voltage. The PGOOD pin is an
undefined impedance if V CC has not reached the rising POR
threshold V CCR , or if V CC is below the falling POR threshold
V CCF . The ISL6268 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During
soft-start or if an undervoltage fault occurs, the PGOOD
pull-down resistance is 95 ? , or 32 ? for an overcurrent fault,
or 63 ? for an overvoltage fault.
PWM
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
7
FN6348.0
August 22, 2006
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